From ad5af8fed14dffba339eaad1e80c4a9e834aa11a Mon Sep 17 00:00:00 2001 From: lkcl Date: Mon, 16 Aug 2021 16:50:26 +0100 Subject: [PATCH] --- openpower/sv/branches.mdwn | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/openpower/sv/branches.mdwn b/openpower/sv/branches.mdwn index 5bf1f0fc3..5ded5ded2 100644 --- a/openpower/sv/branches.mdwn +++ b/openpower/sv/branches.mdwn @@ -79,7 +79,9 @@ Vector Processing. The reason is to have strictly-defined guaranteed behaviour*) In Vertical-First Mode, the `ALL` bit still applies, but to the elements -that are executed up to the Hint length, in parallel batches. See +that are executed up to the Hint length, in parallel batches. Contrast +this with Horizontal-First Mode which tests elements from +`0..VL-1`, Vertical-First tests elements `srcstep..MIN(srcstep+VFHint,VL-1)` See [[sv/setvl]] for the definition of Vertical-First Hint. Predication in both INT and CR modes may be applied to `sv.bc` and other -- 2.30.2