From ad8a2f52ca2ad05128d552ad2bd9b5592a9dd712 Mon Sep 17 00:00:00 2001
From: lkcl <lkcl@web>
Date: Mon, 20 Jun 2022 00:35:11 +0100
Subject: [PATCH]

---
 openpower/sv/vector_ops.mdwn | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/openpower/sv/vector_ops.mdwn b/openpower/sv/vector_ops.mdwn
index 82efc4c3f..68e37fbe2 100644
--- a/openpower/sv/vector_ops.mdwn
+++ b/openpower/sv/vector_ops.mdwn
@@ -199,6 +199,8 @@ pseudocode:
                     setting_mode = True # back into "setting" mode
             i += 1
 
+<https://github.com/riscv-software-src/riscv-isa-sim/blob/master/riscv/insns/vmsbf_m.h>
+
 ## sifm
 
 The vector mask set-including-first instruction is similar to set-before-first, except it also includes the element with a set bit.
-- 
2.30.2