From ad9082fe66ff5f4aeda7cdfa163f5f93e17113bf Mon Sep 17 00:00:00 2001 From: lkcl Date: Fri, 12 Aug 2022 18:37:55 +0100 Subject: [PATCH] --- openpower/sv/ldst.mdwn | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-) diff --git a/openpower/sv/ldst.mdwn b/openpower/sv/ldst.mdwn index b1a8a1b81..6f7cf6edf 100644 --- a/openpower/sv/ldst.mdwn +++ b/openpower/sv/ldst.mdwn @@ -133,7 +133,8 @@ written out in quick succession to a memory-mapped peripheral from sequentially-numbered registers. Note that there are no immediate versions of cache-inhibited LD/ST -(no *Scalar* cache-inhibited immediate instructions to Vectorise) +(no *Scalar* cache-inhibited immediate instructions to Vectorise). +A future version of the Power ISA *may* have such Scalar instructions. **LD/ST Indexed** @@ -173,7 +174,8 @@ all EA computation with elwidth overrides is unsigned. Note that cache-inhibited LD/ST (`ldcix`) when VSPLAT is activated will perform **multiple** LD/ST operations, sequentially. `ldcix` even with scalar src will read the same memory location *multiple times*, storing the result in successive Vector destination registers. This because the cache-inhibit instructions are used to read and write memory-mapped peripherals. If a genuine cache-inhibited LD-VSPLAT is required then a *scalar* -cache-inhibited LD should be performed, followed by a VSPLAT-augmented mv. +cache-inhibited LD should be performed, followed by a VSPLAT-augmented mv, +copying the one *scalar* value into multiple register destinations. Note also that cache-inhibited VSPLAT with Predicate-result is possible. This allows for example to issue a massive batch of memory-mapped @@ -181,6 +183,10 @@ peripheral reads, stopping at the first NULL-terminated character and truncating VL to that point. No branch is needed to issue that large burst of LDs. +The multiple reads/writes to/from the same destination address is, +in Vector-Indexed LD/ST, very similar to the relaxed constraints of +mapreduce mode, + # Vectorisation of Scalar Power ISA v3.0B OpenPOWER Load/Store operations may be seen from [[isa/fixedload]] and -- 2.30.2