From ad974a07efc049c1d72f6c8c06afd12da4462b4d Mon Sep 17 00:00:00 2001 From: Sebastien Bourdeauducq Date: Mon, 6 Jan 2014 22:12:42 +0100 Subject: [PATCH] gensoc: support for user-defined UART and add default values for SRAM and L2 sizes --- misoclib/gensoc/__init__.py | 11 ++++++----- targets/mlabs_video.py | 2 -- targets/simple.py | 3 +-- 3 files changed, 7 insertions(+), 9 deletions(-) diff --git a/misoclib/gensoc/__init__.py b/misoclib/gensoc/__init__.py index 615091a0..7780b068 100644 --- a/misoclib/gensoc/__init__.py +++ b/misoclib/gensoc/__init__.py @@ -14,7 +14,7 @@ class GenSoC(Module): csr_base = 0xe0000000 csr_map = { "crg": 0, # user - "uart": 1, # provided + "uart": 1, # provided by default "identifier": 2, # provided "timer0": 3, # provided "buttons": 4, # user @@ -30,7 +30,7 @@ class GenSoC(Module): "papilio_pro": 0x5050 }) - def __init__(self, platform, clk_freq, cpu_reset_address, sram_size, l2_size=0): + def __init__(self, platform, clk_freq, cpu_reset_address, sram_size=4096, l2_size=0, with_uart=True): self.clk_freq = clk_freq self.cpu_reset_address = cpu_reset_address self.sram_size = sram_size @@ -54,7 +54,8 @@ class GenSoC(Module): self.add_cpu_memory_region("sram", 0x10000000, sram_size) # CSR - self.submodules.uart = uart.UART(platform.request("serial"), clk_freq, baud=115200) + if with_uart: + self.submodules.uart = uart.UART(platform.request("serial"), clk_freq, baud=115200) self.submodules.identifier = identifier.Identifier(self.known_platform_id[platform.name], int(clk_freq), log2_int(l2_size) if l2_size else 0) self.submodules.timer0 = timer.Timer() @@ -130,8 +131,8 @@ class SDRAMSoC(GenSoC): } csr_map.update(GenSoC.csr_map) - def __init__(self, platform, clk_freq, cpu_reset_address, sram_size, l2_size, with_memtest): - GenSoC.__init__(self, platform, clk_freq, cpu_reset_address, sram_size, l2_size) + def __init__(self, platform, clk_freq, cpu_reset_address, with_memtest=False, sram_size=4096, l2_size=8192, with_uart=True): + GenSoC.__init__(self, platform, clk_freq, cpu_reset_address, sram_size, l2_size, with_uart) self.with_memtest = with_memtest self._sdram_phy_registered = False diff --git a/targets/mlabs_video.py b/targets/mlabs_video.py index 57694990..6533fe06 100644 --- a/targets/mlabs_video.py +++ b/targets/mlabs_video.py @@ -46,8 +46,6 @@ class MiniSoC(SDRAMSoC): SDRAMSoC.__init__(self, platform, clk_freq=(83 + Fraction(1, 3))*1000000, cpu_reset_address=0x00180000, - sram_size=4096, - l2_size=8192, with_memtest=with_memtest) sdram_geom = lasmicon.GeomSettings( diff --git a/targets/simple.py b/targets/simple.py index 90c65d4b..eb838a6a 100644 --- a/targets/simple.py +++ b/targets/simple.py @@ -7,8 +7,7 @@ class SimpleSoC(GenSoC, IntegratedBIOS): def __init__(self, platform): GenSoC.__init__(self, platform, clk_freq=32*1000000, - cpu_reset_address=0, - sram_size=4096) + cpu_reset_address=0) IntegratedBIOS.__init__(self) # We can't use reset_less as LM32 does require a reset signal -- 2.30.2