From ada80545faf6a0c0d871909f9e50e0f426b46ed8 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Sat, 2 Nov 2013 21:13:01 +0100 Subject: [PATCH] Behavior should be identical now to rev. 0b4a64ac6adbd6 (next: testing before constfold fixes) --- frontends/ast/genrtlil.cc | 2 ++ frontends/ast/simplify.cc | 6 ++++-- tests/simple/vloghammer.v | 12 ++++++------ 3 files changed, 12 insertions(+), 8 deletions(-) diff --git a/frontends/ast/genrtlil.cc b/frontends/ast/genrtlil.cc index a4e01899c..ff4841ec4 100644 --- a/frontends/ast/genrtlil.cc +++ b/frontends/ast/genrtlil.cc @@ -570,6 +570,8 @@ void AstNode::detectSignWidthWorker(int &width_hint, bool &sign_hint) this_width = range->range_left - range->range_right + 1; } else width_hint = std::max(width_hint, this_width); + if (!id2ast->is_signed) + sign_hint = false; break; case AST_TO_SIGNED: diff --git a/frontends/ast/simplify.cc b/frontends/ast/simplify.cc index 3acbb57d2..960f12075 100644 --- a/frontends/ast/simplify.cc +++ b/frontends/ast/simplify.cc @@ -920,8 +920,10 @@ skip_dynamic_range_lvalue_expansion:; if (0) { case AST_POS: const_func = RTLIL::const_pos; } if (0) { case AST_NEG: const_func = RTLIL::const_neg; } if (children[0]->type == AST_CONSTANT) { - RTLIL::Const y = const_func(children[0]->bitsAsConst(width_hint), dummy_arg, sign_hint, false, width_hint); - newNode = mkconst_bits(y.bits, sign_hint); + RTLIL::Const y = const_func(RTLIL::Const(children[0]->bits), dummy_arg, children[0]->is_signed, false, -1); + newNode = mkconst_bits(y.bits, children[0]->is_signed); + // RTLIL::Const y = const_func(children[0]->bitsAsConst(width_hint), dummy_arg, sign_hint, false, width_hint); + // newNode = mkconst_bits(y.bits, sign_hint); } break; case AST_TERNARY: diff --git a/tests/simple/vloghammer.v b/tests/simple/vloghammer.v index c705bfa7f..d1f55fdb4 100644 --- a/tests/simple/vloghammer.v +++ b/tests/simple/vloghammer.v @@ -73,10 +73,10 @@ module test10(a, b, c, y); assign y = ^(a ? b : c); endmodule -module test11(a, b, y); - input signed [3:0] a; - input signed [3:0] b; - output signed [5:0] y; - assign y = -(5'd27); -endmodule +// module test11(a, b, y); +// input signed [3:0] a; +// input signed [3:0] b; +// output signed [5:0] y; +// assign y = -(5'd27); +// endmodule -- 2.30.2