From adc34689dd877f322c052d5c29fc77af991e7a5d Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Wed, 1 Jul 2020 20:38:00 +0100 Subject: [PATCH] minor reorg on how Bus and Config classes are set up --- src/soc/bus/test/test_minerva.py | 8 ++++---- src/soc/config/ifetch.py | 3 +-- src/soc/config/loadstore.py | 4 +--- src/soc/config/test/test_loadstore.py | 3 ++- src/soc/config/test/test_pi2ls.py | 1 + src/soc/experiment/imem.py | 6 +++--- src/soc/minerva/units/fetch.py | 25 +++++++++++++------------ src/soc/minerva/units/loadstore.py | 21 +++++++++++---------- src/soc/minerva/wishbone.py | 13 ++++++------- 9 files changed, 42 insertions(+), 42 deletions(-) diff --git a/src/soc/bus/test/test_minerva.py b/src/soc/bus/test/test_minerva.py index c2bc0d4f..02c83281 100644 --- a/src/soc/bus/test/test_minerva.py +++ b/src/soc/bus/test/test_minerva.py @@ -5,8 +5,8 @@ from soc.minerva.units.fetch import BareFetchUnit, CachedFetchUnit class TestSRAMBareLoadStoreUnit(BareLoadStoreUnit): - def __init__(self, addr_wid=64, mask_wid=4, data_wid=64): - super().__init__(addr_wid, mask_wid, data_wid) + def __init__(self, pspec): + super().__init__(pspec) def elaborate(self, platform): m = super().elaborate(platform) @@ -35,8 +35,8 @@ class TestSRAMBareLoadStoreUnit(BareLoadStoreUnit): class TestSRAMBareFetchUnit(BareFetchUnit): - def __init__(self, addr_wid=64, data_wid=64): - super().__init__(addr_wid, data_wid) + def __init__(self, pspec): + super().__init__(pspec) # small 16-entry Memory self.mem = Memory(width=self.data_wid, depth=32) diff --git a/src/soc/config/ifetch.py b/src/soc/config/ifetch.py index f558d779..8c56d904 100644 --- a/src/soc/config/ifetch.py +++ b/src/soc/config/ifetch.py @@ -17,6 +17,5 @@ class ConfigFetchUnit: #'test_cache_wb': TestCacheFetchUnit } fukls = fudict[pspec.imem_ifacetype] - self.fu = fukls(addr_wid=pspec.addr_wid, # address range - data_wid=pspec.reg_wid) # data bus width + self.fu = fukls(pspec) diff --git a/src/soc/config/loadstore.py b/src/soc/config/loadstore.py index 104483d1..f2361a67 100644 --- a/src/soc/config/loadstore.py +++ b/src/soc/config/loadstore.py @@ -18,9 +18,7 @@ class ConfigLoadStoreUnit: #'test_cache_wb': TestCacheLoadStoreUnit } lsikls = lsidict[pspec.ldst_ifacetype] - self.lsi = lsikls(addr_wid=pspec.addr_wid, # address range - mask_wid=pspec.mask_wid, # cache line range - data_wid=pspec.reg_wid) # data bus width + self.lsi = lsikls(pspec) class ConfigMemoryPortInterface: diff --git a/src/soc/config/test/test_loadstore.py b/src/soc/config/test/test_loadstore.py index d70c3807..1676967a 100644 --- a/src/soc/config/test/test_loadstore.py +++ b/src/soc/config/test/test_loadstore.py @@ -79,7 +79,8 @@ def read_byte(dut, addr): def tst_lsmemtype(ifacetype): m = Module() - pspec = TestMemPspec(ldst_ifacetype=ifacetype, addr_wid=64, + pspec = TestMemPspec(ldst_ifacetype=ifacetype, + imem_ifacetype='' , addr_wid=64, mask_wid=4, reg_wid=32) dut = ConfigLoadStoreUnit(pspec).lsi diff --git a/src/soc/config/test/test_pi2ls.py b/src/soc/config/test/test_pi2ls.py index 6e0b5911..dd60d062 100644 --- a/src/soc/config/test/test_pi2ls.py +++ b/src/soc/config/test/test_pi2ls.py @@ -113,6 +113,7 @@ def tst_config_pi(testcls, ifacetype): """ dut = Module() pspec = TestMemPspec(ldst_ifacetype=ifacetype, + imem_ifacetype='', addr_wid=48, mask_wid=8, reg_wid=64) diff --git a/src/soc/experiment/imem.py b/src/soc/experiment/imem.py index 068a0408..6b51ed77 100644 --- a/src/soc/experiment/imem.py +++ b/src/soc/experiment/imem.py @@ -6,9 +6,9 @@ from nmigen.cli import rtlil class TestMemFetchUnit(FetchUnitInterface, Elaboratable): - def __init__(self, addr_wid=32, data_wid=32): - print ("testmemfetchunit", addr_wid, data_wid) - super().__init__(addr_wid=addr_wid, data_wid=data_wid) + def __init__(self, pspec): + print ("testmemfetchunit", pspec.addr_wid, pspec.reg_wid) + super().__init__(pspec) # limit TestMemory to 2^6 entries of regwid size self.mem = TestMemory(self.data_wid, 6, readonly=True) diff --git a/src/soc/minerva/units/fetch.py b/src/soc/minerva/units/fetch.py index 246f3dda..98259a9b 100644 --- a/src/soc/minerva/units/fetch.py +++ b/src/soc/minerva/units/fetch.py @@ -9,15 +9,16 @@ __all__ = ["FetchUnitInterface", "BareFetchUnit", "CachedFetchUnit"] class FetchUnitInterface: - def __init__(self, addr_wid=32, data_wid=32): - self.addr_wid = addr_wid - self.data_wid = data_wid - self.adr_lsbs = log2_int(data_wid//8) - self.ibus = Record(make_wb_layout(addr_wid, data_wid//8, data_wid)) - bad_wid = addr_wid - self.adr_lsbs # TODO: is this correct? + def __init__(self, pspec): + self.pspec = pspec + self.addr_wid = pspec.addr_wid + self.data_wid = pspec.reg_wid + self.adr_lsbs = log2_int(pspec.reg_wid//8) + self.ibus = Record(make_wb_layout(pspec)) + bad_wid = pspec.addr_wid - self.adr_lsbs # TODO: is this correct? # inputs: address to fetch PC, and valid/stall signalling - self.a_pc_i = Signal(addr_wid) + self.a_pc_i = Signal(self.addr_wid) self.a_stall_i = Signal() self.a_valid_i = Signal() self.f_stall_i = Signal() @@ -26,7 +27,7 @@ class FetchUnitInterface: # outputs: instruction (or error), and busy indicators self.a_busy_o = Signal() self.f_busy_o = Signal() - self.f_instr_o = Signal(data_wid) + self.f_instr_o = Signal(self.data_wid) self.f_fetch_err_o = Signal() self.f_badaddr_o = Signal(bad_wid) @@ -75,10 +76,10 @@ class BareFetchUnit(FetchUnitInterface, Elaboratable): class CachedFetchUnit(FetchUnitInterface, Elaboratable): - def __init__(self, *icache_args, addr_wid=32, data_wid=32): - super().__init__(addr_wid=addr_wid, data_wid=data_wid) + def __init__(self, pspec): + super().__init__(pspec) - self.icache_args = icache_args + self.icache_args = pspec.icache_args self.a_flush = Signal() self.f_pc = Signal(addr_wid) @@ -107,7 +108,7 @@ class CachedFetchUnit(FetchUnitInterface, Elaboratable): icache.s2_valid.eq(self.f_valid_i & f_icache_select) ] - iba = WishboneArbiter(self.addr_wid, self.adr_lsbs, self.data_wid) + iba = WishboneArbiter(self.pspec) m.submodules.ibus_arbiter = iba m.d.comb += iba.bus.connect(self.ibus) diff --git a/src/soc/minerva/units/loadstore.py b/src/soc/minerva/units/loadstore.py index e9a35609..6cd7f889 100644 --- a/src/soc/minerva/units/loadstore.py +++ b/src/soc/minerva/units/loadstore.py @@ -11,13 +11,14 @@ __all__ = ["LoadStoreUnitInterface", "BareLoadStoreUnit", class LoadStoreUnitInterface: - def __init__(self, addr_wid=32, mask_wid=4, data_wid=32): - print ("loadstoreunit addr mask data", addr_wid, mask_wid, data_wid) - self.dbus = Record(make_wb_layout(addr_wid, mask_wid, data_wid)) + def __init__(self, pspec): + self.pspec = pspec + self.dbus = Record(make_wb_layout(pspec)) print (self.dbus.sel.shape()) - self.mask_wid = mask_wid - self.addr_wid = addr_wid - self.data_wid = data_wid + self.mask_wid = mask_wid = pspec.mask_wid + self.addr_wid = addr_wid = pspec.addr_wid + self.data_wid = data_wid = pspec.reg_wid + print ("loadstoreunit addr mask data", addr_wid, mask_wid, data_wid) self.adr_lsbs = log2_int(mask_wid) # LSBs of addr covered by mask badwid = addr_wid-self.adr_lsbs # TODO: is this correct? @@ -104,10 +105,10 @@ class BareLoadStoreUnit(LoadStoreUnitInterface, Elaboratable): class CachedLoadStoreUnit(LoadStoreUnitInterface, Elaboratable): - def __init__(self, *dcache_args, addr_wid=32, mask_wid=4, data_wid=32): - super().__init__(addr_wid, mask_wid, data_wid) + def __init__(self, pspec): + super().__init__(pspec) - self.dcache_args = dcache_args + self.dcache_args = psiec.dcache_args self.x_fence_i = Signal() self.x_flush = Signal() @@ -155,7 +156,7 @@ class CachedLoadStoreUnit(LoadStoreUnitInterface, Elaboratable): wrbuf_r_data.eq(wrbuf.r_data), ] - dba = WishboneArbiter(self.addr_wid, self.mask_wid, self.data_wid) + dba = WishboneArbiter(self.pspec) m.submodules.dbus_arbiter = dba m.d.comb += dba.bus.connect(self.dbus) diff --git a/src/soc/minerva/wishbone.py b/src/soc/minerva/wishbone.py index 27176786..ba08531e 100644 --- a/src/soc/minerva/wishbone.py +++ b/src/soc/minerva/wishbone.py @@ -4,7 +4,7 @@ from nmigen.lib.coding import PriorityEncoder from nmigen.utils import log2_int -__all__ = ["Cycle", "wishbone_layout", "make_wb_layout", "WishboneArbiter"] +__all__ = ["Cycle", "make_wb_layout", "WishboneArbiter"] class Cycle: @@ -14,9 +14,10 @@ class Cycle: END = 7 -def make_wb_layout(addr_wid, mask_wid, data_wid): +def make_wb_layout(spec): + addr_wid, mask_wid, data_wid = spec.addr_wid, spec.mask_wid, spec.reg_wid adr_lsbs = log2_int(mask_wid) # LSBs of addr covered by mask - badwid = addr_wid-adr_lsbs # MSBs (not covered by mask) + badwid = spec.addr_wid-adr_lsbs # MSBs (not covered by mask) return [ ("adr", badwid , DIR_FANOUT), @@ -32,12 +33,10 @@ def make_wb_layout(addr_wid, mask_wid, data_wid): ("err", 1, DIR_FANIN) ] -wishbone_layout = make_wb_layout(32, 4, 32) - class WishboneArbiter(Elaboratable): - def __init__(self, addr_wid=32, mask_wid=4, data_wid=32): - self.bus = Record(make_wb_layout(addr_wid, mask_wid, data_wid)) + def __init__(self, pspec): + self.bus = Record(make_wb_layout(pspec)) self._port_map = dict() def port(self, priority): -- 2.30.2