From add5a87a46cb4699f6d812a9b9f462dbc7184f86 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Wed, 5 May 2021 16:33:48 +0100 Subject: [PATCH] if zeroing is set, put zero into input or output as requested --- src/soc/fu/common_input_stage.py | 8 ++++++-- src/soc/fu/common_output_stage.py | 10 ++++++---- 2 files changed, 12 insertions(+), 6 deletions(-) diff --git a/src/soc/fu/common_input_stage.py b/src/soc/fu/common_input_stage.py index 09a02006..53e023ad 100644 --- a/src/soc/fu/common_input_stage.py +++ b/src/soc/fu/common_input_stage.py @@ -31,7 +31,9 @@ class CommonInputStage(PipeModBase): else: comb += a.eq(self.i.a) - comb += self.o.a.eq(a) + # SV zeroing on predicate source zeros the input + with m.If(~op.sv_pred_sz): + comb += self.o.a.eq(a) ##### operand B ##### @@ -46,7 +48,9 @@ class CommonInputStage(PipeModBase): else: comb += b.eq(self.i.b) - comb += self.o.b.eq(b) + # SV zeroing on predicate source zeros the input + with m.If(~op.sv_pred_sz): + comb += self.o.b.eq(b) ##### carry-in ##### diff --git a/src/soc/fu/common_output_stage.py b/src/soc/fu/common_output_stage.py index e5cf3a30..23e83f57 100644 --- a/src/soc/fu/common_output_stage.py +++ b/src/soc/fu/common_output_stage.py @@ -87,11 +87,13 @@ class CommonOutputStage(PipeModBase): with m.Else(): comb += cr0.eq(Cat(so, ~is_nzero, is_positive, is_negative)) - # copy out [inverted?] output, cr0, and context out - comb += self.o.o.data.eq(o) + with m.If(~op.sv_pred_dz): + # copy out [inverted?] output, cr0, and context out + comb += self.o.o.data.eq(o) + comb += self.o.cr0.data.eq(cr0) # CR0 to be set + + # set output to write comb += self.o.o.ok.eq(self.i.o.ok) - # CR0 to be set - comb += self.o.cr0.data.eq(cr0) comb += self.o.cr0.ok.eq(op.write_cr0) # context comb += self.o.ctx.eq(self.i.ctx) -- 2.30.2