From adf94fdfd40b1a7b4714b07c6157068c0318c0fc Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Wed, 17 Mar 2021 12:34:04 +0000 Subject: [PATCH] add instr_fetch mode to ISACaller Mem and RADIXMMU --- src/soc/decoder/isa/caller.py | 8 +++++--- src/soc/decoder/isa/mem.py | 6 ++++-- src/soc/decoder/isa/radixmmu.py | 12 ++++++++---- 3 files changed, 17 insertions(+), 9 deletions(-) diff --git a/src/soc/decoder/isa/caller.py b/src/soc/decoder/isa/caller.py index b7f8ac6d..2bc5b640 100644 --- a/src/soc/decoder/isa/caller.py +++ b/src/soc/decoder/isa/caller.py @@ -411,9 +411,11 @@ class ISACaller: self.gpr = GPR(decoder2, self, self.svstate, regfile) self.spr = SPR(decoder2, initial_sprs) # initialise SPRs before MMU self.mem = Mem(row_bytes=8, initial_mem=initial_mem) + self.imem = Mem(row_bytes=4, initial_mem=initial_insns) + # MMU mode, redirect underlying Mem through RADIX if mmu: self.mem = RADIX(self.mem, self) - self.imem = Mem(row_bytes=4, initial_mem=initial_insns) + self.imem = RADIX(self.imem, self) self.pc = PC() self.msr = SelectableInt(initial_msr, 64) # underlying reg @@ -652,7 +654,7 @@ class ISACaller: else: pc = self.fake_pc self._pc = pc - ins = self.imem.ld(pc, 4, False, True) + ins = self.imem.ld(pc, 4, False, True, instr_fetch=True) if ins is None: raise KeyError("no instruction at 0x%x" % pc) print("setup: 0x%x 0x%x %s" % (pc, ins & 0xffffffff, bin(ins))) @@ -688,7 +690,7 @@ class ISACaller: print (" svstate.vl", self.svstate.vl.asint(msb0=True)) print (" svstate.mvl", self.svstate.maxvl.asint(msb0=True)) sv_rm = pfx.rm.asint(msb0=True) - ins = self.imem.ld(pc+4, 4, False, True) + ins = self.imem.ld(pc+4, 4, False, True, instr_fetch=True) print(" svsetup: 0x%x 0x%x %s" % (pc+4, ins & 0xffffffff, bin(ins))) yield self.dec2.dec.raw_opcode_in.eq(ins & 0xffffffff) # v3.0B suffix yield self.dec2.sv_rm.eq(sv_rm) # svp64 prefix diff --git a/src/soc/decoder/isa/mem.py b/src/soc/decoder/isa/mem.py index 723fca09..7a806a40 100644 --- a/src/soc/decoder/isa/mem.py +++ b/src/soc/decoder/isa/mem.py @@ -64,8 +64,10 @@ class Mem: return shifter, mask # TODO: Implement ld/st of lesser width - def ld(self, address, width=8, swap=True, check_in_mem=False): - print("ld from addr 0x{:x} width {:d}".format(address, width)) + def ld(self, address, width=8, swap=True, check_in_mem=False, + instr_fetch=False): + print("ld from addr 0x{:x} width {:d}".format(address, width), + swap, check_in_mem, instr_fetch) remainder = address & (self.bytes_per_word - 1) address = address >> self.word_log2 assert remainder & (width - 1) == 0, "Unaligned access unsupported!" diff --git a/src/soc/decoder/isa/radixmmu.py b/src/soc/decoder/isa/radixmmu.py index 528932b8..688d20fe 100644 --- a/src/soc/decoder/isa/radixmmu.py +++ b/src/soc/decoder/isa/radixmmu.py @@ -212,10 +212,14 @@ class RADIX: print("RADIX memread", addr, sz, val) return SelectableInt(val, sz*8) - def ld(self, address, width=8, swap=True, check_in_mem=False): + def ld(self, address, width=8, swap=True, check_in_mem=False, + instr_fetch=False): print("RADIX: ld from addr 0x%x width %d" % (address, width)) - mode = 'LOAD' # XXX TODO: executable load (icache) + if instr_fetch: + mode = 'EXECUTE' + else: + mode = 'LOAD' addr = SelectableInt(address, 64) (shift, mbits, pgbase) = self._decode_prte(addr) #shift = SelectableInt(0, 32) @@ -426,7 +430,7 @@ class RADIX: new_shift = shift + (31 - 12) - mbits return new_shift - def _check_perms(self, data, priv, iside, store): + def _check_perms(self, data, priv, instr_fetch, store): """check page permissions // Leaf PDE | // |------------------------------| |----------------| @@ -474,7 +478,7 @@ class RADIX: # check permissions and RC bits perm_ok = 0 if priv == 1 or data[60] == 0: - if iside == 0: + if instr_fetch == 0: perm_ok = data[62] | (data[61] & (store == 0)) # no IAMR, so no KUEP support for now # deny execute permission if cache inhibited -- 2.30.2