From ae02d9cb9a990bfbe76d056fd341d88a9a5f129c Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Tue, 16 Sep 2014 12:40:58 +0200 Subject: [PATCH] Fixed $memwr/$memrd order in memory_dff --- passes/memory/memory_dff.cc | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) diff --git a/passes/memory/memory_dff.cc b/passes/memory/memory_dff.cc index cdd0b85e2..302ab3abf 100644 --- a/passes/memory/memory_dff.cc +++ b/passes/memory/memory_dff.cc @@ -169,12 +169,14 @@ static void handle_module(RTLIL::Module *module, bool flag_wr_only) if (cell->type == "$dff") dff_cells.push_back(cell); - for (auto cell : module->selected_cells()) { + for (auto cell : module->selected_cells()) if (cell->type == "$memwr" && !cell->parameters["\\CLK_ENABLE"].as_bool()) - handle_wr_cell(module, dff_cells, cell); - if (!flag_wr_only && cell->type == "$memrd" && !cell->parameters["\\CLK_ENABLE"].as_bool()) + handle_wr_cell(module, dff_cells, cell); + + if (!flag_wr_only) + for (auto cell : module->selected_cells()) + if (cell->type == "$memrd" && !cell->parameters["\\CLK_ENABLE"].as_bool()) handle_rd_cell(module, dff_cells, cell); - } } struct MemoryDffPass : public Pass { -- 2.30.2