From ae203c6ecda472611e2ff684a348c6b189192e4e Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Wed, 8 May 2019 03:12:49 +0100 Subject: [PATCH] replace go_read/go_write with go_rd/go_wr --- src/scoreboard/dependence_cell.py | 34 +++++++++++++++---------------- src/scoreboard/fn_unit.py | 24 +++++++++++----------- src/scoreboard/fu_dep_cell.py | 24 +++++++++++----------- src/scoreboard/fu_fu_matrix.py | 32 ++++++++++++++--------------- src/scoreboard/fu_reg_matrix.py | 30 +++++++++++++-------------- src/scoreboard/global_pending.py | 8 ++++---- src/scoreboard/group_picker.py | 8 ++++---- src/scoreboard/issue_unit.py | 8 ++++---- src/scoreboard/ldst_dep_cell.py | 8 ++++---- src/scoreboard/ldst_matrix.py | 8 ++++---- src/scoreboard/shadow_fn.py | 8 ++++---- 11 files changed, 96 insertions(+), 96 deletions(-) diff --git a/src/scoreboard/dependence_cell.py b/src/scoreboard/dependence_cell.py index 18e8d755..5b7baea8 100644 --- a/src/scoreboard/dependence_cell.py +++ b/src/scoreboard/dependence_cell.py @@ -14,8 +14,8 @@ class DependenceCell(Elaboratable): self.src2_i = Signal(reset_less=True) # oper2 in (top) self.issue_i = Signal(reset_less=True) # Issue in (top) - self.go_write_i = Signal(reset_less=True) # Go Write in (left) - self.go_read_i = Signal(reset_less=True) # Go Read in (left) + self.go_wr_i = Signal(reset_less=True) # Go Write in (left) + self.go_rd_i = Signal(reset_less=True) # Go Read in (left) # for Register File Select Lines (vertical) self.dest_rsel_o = Signal(reset_less=True) # dest reg sel (bottom) @@ -33,17 +33,17 @@ class DependenceCell(Elaboratable): m.submodules.src1_l = src1_l = SRLatch() m.submodules.src2_l = src2_l = SRLatch() - # destination latch: reset on go_write HI, set on dest and issue + # destination latch: reset on go_wr HI, set on dest and issue m.d.comb += dest_l.s.eq(self.issue_i & self.dest_i) - m.d.comb += dest_l.r.eq(self.go_write_i) + m.d.comb += dest_l.r.eq(self.go_wr_i) - # src1 latch: reset on go_read HI, set on src1_i and issue + # src1 latch: reset on go_rd HI, set on src1_i and issue m.d.comb += src1_l.s.eq(self.issue_i & self.src1_i) - m.d.comb += src1_l.r.eq(self.go_read_i) + m.d.comb += src1_l.r.eq(self.go_rd_i) - # src2 latch: reset on go_read HI, set on op2_i and issue + # src2 latch: reset on go_rd HI, set on op2_i and issue m.d.comb += src2_l.s.eq(self.issue_i & self.src2_i) - m.d.comb += src2_l.r.eq(self.go_read_i) + m.d.comb += src2_l.r.eq(self.go_rd_i) # FU "Forward Progress" (read out horizontally) m.d.comb += self.dest_fwd_o.eq(dest_l.qn & self.dest_i) @@ -51,9 +51,9 @@ class DependenceCell(Elaboratable): m.d.comb += self.src2_fwd_o.eq(src2_l.qn & self.src2_i) # Register File Select (read out vertically) - m.d.comb += self.dest_rsel_o.eq(dest_l.qn & self.go_write_i) - m.d.comb += self.src1_rsel_o.eq(src1_l.qn & self.go_read_i) - m.d.comb += self.src2_rsel_o.eq(src2_l.qn & self.go_read_i) + m.d.comb += self.dest_rsel_o.eq(dest_l.qn & self.go_wr_i) + m.d.comb += self.src1_rsel_o.eq(src1_l.qn & self.go_rd_i) + m.d.comb += self.src2_rsel_o.eq(src2_l.qn & self.go_rd_i) return m @@ -62,8 +62,8 @@ class DependenceCell(Elaboratable): yield self.src1_i yield self.src2_i yield self.issue_i - yield self.go_write_i - yield self.go_read_i + yield self.go_wr_i + yield self.go_rd_i yield self.dest_rsel_o yield self.src1_rsel_o yield self.src2_rsel_o @@ -88,13 +88,13 @@ def dcell_sim(dut): yield yield dut.issue_i.eq(0) yield - yield dut.go_read_i.eq(1) + yield dut.go_rd_i.eq(1) yield - yield dut.go_read_i.eq(0) + yield dut.go_rd_i.eq(0) yield - yield dut.go_write_i.eq(1) + yield dut.go_wr_i.eq(1) yield - yield dut.go_write_i.eq(0) + yield dut.go_wr_i.eq(0) yield def test_dcell(): diff --git a/src/scoreboard/fn_unit.py b/src/scoreboard/fn_unit.py index 8474e2dc..bbb60ac5 100644 --- a/src/scoreboard/fn_unit.py +++ b/src/scoreboard/fn_unit.py @@ -50,8 +50,8 @@ class FnUnit(Elaboratable): self.src2_i = Signal(max=wid, reset_less=True) # oper2 R# in (top) self.issue_i = Signal(reset_less=True) # Issue in (top) - self.go_write_i = Signal(reset_less=True) # Go Write in (left) - self.go_read_i = Signal(reset_less=True) # Go Read in (left) + self.go_wr_i = Signal(reset_less=True) # Go Write in (left) + self.go_rd_i = Signal(reset_less=True) # Go Read in (left) self.req_rel_i = Signal(reset_less=True) # request release (left) self.g_xx_pend_i = Array(Signal(wid, reset_less=True, name="g_pend_i") \ @@ -124,13 +124,13 @@ class FnUnit(Elaboratable): m.d.comb += self.xx_pend_o[i].eq(0) # initialise all array m.d.comb += self.writable_o[i].eq(0) # to zero - # go_write latch: reset on go_write HI, set on issue + # go_wr latch: reset on go_wr HI, set on issue m.d.comb += wr_l.s.eq(self.issue_i) - m.d.comb += wr_l.r.eq(self.go_write_i | recover) + m.d.comb += wr_l.r.eq(self.go_wr_i | recover) - # src1 latch: reset on go_read HI, set on issue + # src1 latch: reset on go_rd HI, set on issue m.d.comb += rd_l.s.eq(self.issue_i) - m.d.comb += rd_l.r.eq(self.go_read_i | recover) + m.d.comb += rd_l.r.eq(self.go_rd_i | recover) # dest decoder: write-pending out m.d.comb += dest_d.i.eq(self.dest_i) @@ -166,8 +166,8 @@ class FnUnit(Elaboratable): yield self.src1_i yield self.src2_i yield self.issue_i - yield self.go_write_i - yield self.go_read_i + yield self.go_wr_i + yield self.go_rd_i yield self.req_rel_i yield from self.g_xx_pend_i yield self.g_wr_pend_i @@ -296,13 +296,13 @@ def int_fn_unit_sim(dut): yield yield dut.issue_i.eq(0) yield - yield dut.go_read_i.eq(1) + yield dut.go_rd_i.eq(1) yield - yield dut.go_read_i.eq(0) + yield dut.go_rd_i.eq(0) yield - yield dut.go_write_i.eq(1) + yield dut.go_wr_i.eq(1) yield - yield dut.go_write_i.eq(0) + yield dut.go_wr_i.eq(0) yield def test_int_fn_unit(): diff --git a/src/scoreboard/fu_dep_cell.py b/src/scoreboard/fu_dep_cell.py index 93ef28d3..250ba85b 100644 --- a/src/scoreboard/fu_dep_cell.py +++ b/src/scoreboard/fu_dep_cell.py @@ -13,8 +13,8 @@ class FUDependenceCell(Elaboratable): self.wr_pend_i = Signal(reset_less=True) # write pending in (left) self.issue_i = Signal(reset_less=True) # Issue in (top) - self.go_write_i = Signal(reset_less=True) # Go Write in (left) - self.go_read_i = Signal(reset_less=True) # Go Read in (left) + self.go_wr_i = Signal(reset_less=True) # Go Write in (left) + self.go_rd_i = Signal(reset_less=True) # Go Read in (left) # outputs (latched rd/wr pend) self.rd_pend_o = Signal(reset_less=True) # read pending out (right) @@ -25,13 +25,13 @@ class FUDependenceCell(Elaboratable): m.submodules.rd_l = rd_l = SRLatch() m.submodules.wr_l = wr_l = SRLatch() - # write latch: reset on go_write HI, set on write pending and issue + # write latch: reset on go_wr HI, set on write pending and issue m.d.comb += wr_l.s.eq(self.issue_i & self.wr_pend_i) - m.d.comb += wr_l.r.eq(self.go_write_i) + m.d.comb += wr_l.r.eq(self.go_wr_i) - # read latch: reset on go_read HI, set on read pending and issue + # read latch: reset on go_rd HI, set on read pending and issue m.d.comb += rd_l.s.eq(self.issue_i & self.rd_pend_i) - m.d.comb += rd_l.r.eq(self.go_read_i) + m.d.comb += rd_l.r.eq(self.go_rd_i) # Read/Write Pending Latches (read out horizontally) m.d.comb += self.wr_pend_o.eq(wr_l.qn) @@ -43,8 +43,8 @@ class FUDependenceCell(Elaboratable): yield self.rd_pend_i yield self.wr_pend_i yield self.issue_i - yield self.go_write_i - yield self.go_read_i + yield self.go_wr_i + yield self.go_rd_i yield self.rd_pend_o yield self.wr_pend_o @@ -63,13 +63,13 @@ def dcell_sim(dut): yield yield dut.issue_i.eq(0) yield - yield dut.go_read_i.eq(1) + yield dut.go_rd_i.eq(1) yield - yield dut.go_read_i.eq(0) + yield dut.go_rd_i.eq(0) yield - yield dut.go_write_i.eq(1) + yield dut.go_wr_i.eq(1) yield - yield dut.go_write_i.eq(0) + yield dut.go_wr_i.eq(0) yield def test_dcell(): diff --git a/src/scoreboard/fu_fu_matrix.py b/src/scoreboard/fu_fu_matrix.py index b558927c..a73cde9c 100644 --- a/src/scoreboard/fu_fu_matrix.py +++ b/src/scoreboard/fu_fu_matrix.py @@ -23,8 +23,8 @@ class FUFUDepMatrix(Elaboratable): self.wr_pend_i = Signal(n_fu_row, reset_less=True) # Wr pending (left) self.issue_i = Signal(n_fu_col, reset_less=True) # Issue in (top) - self.go_write_i = Signal(n_fu_row, reset_less=True) # Go Write in (left) - self.go_read_i = Signal(n_fu_row, reset_less=True) # Go Read in (left) + self.go_wr_i = Signal(n_fu_row, reset_less=True) # Go Write in (left) + self.go_rd_i = Signal(n_fu_row, reset_less=True) # Go Read in (left) # for Function Unit Readable/Writable (horizontal) self.readable_o = Signal(n_fu_col, reset_less=True) # readable (bot) @@ -88,23 +88,23 @@ class FUFUDepMatrix(Elaboratable): m.d.comb += Cat(*issue_i).eq(self.issue_i) # --- - # connect Matrix go_read_i/go_write_i to module readable/writable + # connect Matrix go_rd_i/go_wr_i to module readable/writable # --- for x in range(self.n_fu_col): - go_read_i = [] - go_write_i = [] + go_rd_i = [] + go_wr_i = [] rd_pend_i = [] wr_pend_i = [] for y in range(self.n_fu_row): dc = dm[x][y] - # accumulate cell rd_pend/wr_pend/go_read/go_write + # accumulate cell rd_pend/wr_pend/go_rd/go_wr rd_pend_i.append(dc.rd_pend_i) wr_pend_i.append(dc.wr_pend_i) - go_read_i.append(dc.go_read_i) - go_write_i.append(dc.go_write_i) + go_rd_i.append(dc.go_rd_i) + go_wr_i.append(dc.go_wr_i) # wire up inputs from module to row cell inputs (Cat is gooood) - m.d.comb += [Cat(*go_read_i).eq(self.go_read_i), - Cat(*go_write_i).eq(self.go_write_i), + m.d.comb += [Cat(*go_rd_i).eq(self.go_rd_i), + Cat(*go_wr_i).eq(self.go_wr_i), Cat(*rd_pend_i).eq(self.rd_pend_i), Cat(*wr_pend_i).eq(self.wr_pend_i), ] @@ -115,8 +115,8 @@ class FUFUDepMatrix(Elaboratable): yield self.rd_pend_i yield self.wr_pend_i yield self.issue_i - yield self.go_write_i - yield self.go_read_i + yield self.go_wr_i + yield self.go_rd_i yield self.readable_o yield self.writable_o @@ -136,13 +136,13 @@ def d_matrix_sim(dut): yield yield dut.issue_i.eq(0) yield - yield dut.go_read_i.eq(1) + yield dut.go_rd_i.eq(1) yield - yield dut.go_read_i.eq(0) + yield dut.go_rd_i.eq(0) yield - yield dut.go_write_i.eq(1) + yield dut.go_wr_i.eq(1) yield - yield dut.go_write_i.eq(0) + yield dut.go_wr_i.eq(0) yield def test_fu_fu_matrix(): diff --git a/src/scoreboard/fu_reg_matrix.py b/src/scoreboard/fu_reg_matrix.py index 9997d6e2..f28e366f 100644 --- a/src/scoreboard/fu_reg_matrix.py +++ b/src/scoreboard/fu_reg_matrix.py @@ -36,8 +36,8 @@ class FURegDepMatrix(Elaboratable): self.src2_i = Signal(n_reg_col, reset_less=True) # oper2 in (top) self.issue_i = Signal(n_reg_col, reset_less=True) # Issue in (top) - self.go_write_i = Signal(n_fu_row, reset_less=True) # Go Write in (left) - self.go_read_i = Signal(n_fu_row, reset_less=True) # Go Read in (left) + self.go_wr_i = Signal(n_fu_row, reset_less=True) # Go Write in (left) + self.go_rd_i = Signal(n_fu_row, reset_less=True) # Go Read in (left) # for Register File Select Lines (horizontal), per-reg self.dest_rsel_o = Signal(n_reg_col, reset_less=True) # dest reg (bot) @@ -158,19 +158,19 @@ class FURegDepMatrix(Elaboratable): ] # --- - # connect Dependency Matrix go_read_i/go_write_i to module go_rd/go_wr + # connect Dependency Matrix go_rd_i/go_wr_i to module go_rd/go_wr # --- for fu in range(self.n_fu_row): - go_read_i = [] - go_write_i = [] + go_rd_i = [] + go_wr_i = [] for rn in range(self.n_reg_col): dc = dm[rn][fu] # accumulate cell fwd outputs for dest/src1/src2 - go_read_i.append(dc.go_read_i) - go_write_i.append(dc.go_write_i) + go_rd_i.append(dc.go_rd_i) + go_wr_i.append(dc.go_wr_i) # wire up inputs from module to row cell inputs (Cat is gooood) - m.d.comb += [Cat(*go_read_i).eq(self.go_read_i), - Cat(*go_write_i).eq(self.go_write_i), + m.d.comb += [Cat(*go_rd_i).eq(self.go_rd_i), + Cat(*go_wr_i).eq(self.go_wr_i), ] return m @@ -180,8 +180,8 @@ class FURegDepMatrix(Elaboratable): yield self.src1_i yield self.src2_i yield self.issue_i - yield self.go_write_i - yield self.go_read_i + yield self.go_wr_i + yield self.go_rd_i yield self.dest_rsel_o yield self.src1_rsel_o yield self.src2_rsel_o @@ -204,13 +204,13 @@ def d_matrix_sim(dut): yield yield dut.issue_i.eq(0) yield - yield dut.go_read_i.eq(1) + yield dut.go_rd_i.eq(1) yield - yield dut.go_read_i.eq(0) + yield dut.go_rd_i.eq(0) yield - yield dut.go_write_i.eq(1) + yield dut.go_wr_i.eq(1) yield - yield dut.go_write_i.eq(0) + yield dut.go_wr_i.eq(0) yield def test_d_matrix(): diff --git a/src/scoreboard/global_pending.py b/src/scoreboard/global_pending.py index 50e43378..a5d4db1b 100644 --- a/src/scoreboard/global_pending.py +++ b/src/scoreboard/global_pending.py @@ -69,13 +69,13 @@ def g_vec_sim(dut): yield yield dut.issue_i.eq(0) yield - yield dut.go_read_i.eq(1) + yield dut.go_rd_i.eq(1) yield - yield dut.go_read_i.eq(0) + yield dut.go_rd_i.eq(0) yield - yield dut.go_write_i.eq(1) + yield dut.go_wr_i.eq(1) yield - yield dut.go_write_i.eq(0) + yield dut.go_wr_i.eq(0) yield def test_g_vec(): diff --git a/src/scoreboard/group_picker.py b/src/scoreboard/group_picker.py index 8f959a18..78f83414 100644 --- a/src/scoreboard/group_picker.py +++ b/src/scoreboard/group_picker.py @@ -90,13 +90,13 @@ def grp_pick_sim(dut): yield yield dut.issue_i.eq(0) yield - yield dut.go_read_i.eq(1) + yield dut.go_rd_i.eq(1) yield - yield dut.go_read_i.eq(0) + yield dut.go_rd_i.eq(0) yield - yield dut.go_write_i.eq(1) + yield dut.go_wr_i.eq(1) yield - yield dut.go_write_i.eq(0) + yield dut.go_wr_i.eq(0) yield def test_grp_pick(): diff --git a/src/scoreboard/issue_unit.py b/src/scoreboard/issue_unit.py index 7b01e8f4..a677bd6e 100644 --- a/src/scoreboard/issue_unit.py +++ b/src/scoreboard/issue_unit.py @@ -117,13 +117,13 @@ def issue_unit_sim(dut): yield yield dut.issue_i.eq(0) yield - yield dut.go_read_i.eq(1) + yield dut.go_rd_i.eq(1) yield - yield dut.go_read_i.eq(0) + yield dut.go_rd_i.eq(0) yield - yield dut.go_write_i.eq(1) + yield dut.go_wr_i.eq(1) yield - yield dut.go_write_i.eq(0) + yield dut.go_wr_i.eq(0) yield def test_issue_unit(): diff --git a/src/scoreboard/ldst_dep_cell.py b/src/scoreboard/ldst_dep_cell.py index 40e1ffbc..c865bdd8 100644 --- a/src/scoreboard/ldst_dep_cell.py +++ b/src/scoreboard/ldst_dep_cell.py @@ -74,13 +74,13 @@ def dcell_sim(dut): yield yield dut.issue_i.eq(0) yield - yield dut.go_read_i.eq(1) + yield dut.go_rd_i.eq(1) yield - yield dut.go_read_i.eq(0) + yield dut.go_rd_i.eq(0) yield - yield dut.go_write_i.eq(1) + yield dut.go_wr_i.eq(1) yield - yield dut.go_write_i.eq(0) + yield dut.go_wr_i.eq(0) yield def test_dcell(): diff --git a/src/scoreboard/ldst_matrix.py b/src/scoreboard/ldst_matrix.py index b872155d..dc9d7362 100644 --- a/src/scoreboard/ldst_matrix.py +++ b/src/scoreboard/ldst_matrix.py @@ -114,13 +114,13 @@ def d_matrix_sim(dut): yield yield dut.issue_i.eq(0) yield - yield dut.go_read_i.eq(1) + yield dut.go_rd_i.eq(1) yield - yield dut.go_read_i.eq(0) + yield dut.go_rd_i.eq(0) yield - yield dut.go_write_i.eq(1) + yield dut.go_wr_i.eq(1) yield - yield dut.go_write_i.eq(0) + yield dut.go_wr_i.eq(0) yield def test_d_matrix(): diff --git a/src/scoreboard/shadow_fn.py b/src/scoreboard/shadow_fn.py index a60f9d95..75f80513 100644 --- a/src/scoreboard/shadow_fn.py +++ b/src/scoreboard/shadow_fn.py @@ -56,13 +56,13 @@ def shadow_fn_unit_sim(dut): yield yield dut.issue_i.eq(0) yield - yield dut.go_read_i.eq(1) + yield dut.go_rd_i.eq(1) yield - yield dut.go_read_i.eq(0) + yield dut.go_rd_i.eq(0) yield - yield dut.go_write_i.eq(1) + yield dut.go_wr_i.eq(1) yield - yield dut.go_write_i.eq(0) + yield dut.go_wr_i.eq(0) yield -- 2.30.2