From ae266b309180b9b820cc8d4e34133c4e60ae17b2 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Sat, 12 Sep 2020 23:21:22 +0100 Subject: [PATCH] missing reservation address comparison --- src/soc/experiment/dcache.py | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/soc/experiment/dcache.py b/src/soc/experiment/dcache.py index abf6c276..5e797f41 100644 --- a/src/soc/experiment/dcache.py +++ b/src/soc/experiment/dcache.py @@ -935,14 +935,14 @@ class DCache(Elaboratable): sync = m.d.sync with m.If(r0_valid & r0.req.reserve): - # XXX generate alignment interrupt if address # is not aligned XXX or if r0.req.nc = '1' with m.If(r0.req.load): comb += set_rsrv.eq(1) # load with reservation with m.Else(): comb += clear_rsrv.eq(1) # store conditional - with m.If(~reservation.valid | r0.req.addr[LINE_OFF_BITS:64]): + with m.If(~reservation.valid | + (r0.req.addr[LINE_OFF_BITS:64] != reservation.addr)): comb += cancel_store.eq(1) def reservation_reg(self, m, r0_valid, access_ok, set_rsrv, clear_rsrv, -- 2.30.2