From ae45be47734eb2842ccf992954e336cd783c5569 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Tue, 18 Feb 2020 10:15:01 +0100 Subject: [PATCH] soc/cores/clock: add reset_cycles parameter to S7IDELAYCTRL/USIDELAYCTRL --- litex/soc/cores/clock.py | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/litex/soc/cores/clock.py b/litex/soc/cores/clock.py index 9139288e..cab8bfce 100644 --- a/litex/soc/cores/clock.py +++ b/litex/soc/cores/clock.py @@ -292,8 +292,8 @@ class S7MMCM(XilinxClocking): class S7IDELAYCTRL(Module): - def __init__(self, cd): - reset_counter = Signal(4, reset=15) + def __init__(self, cd, reset_cycles=16): + reset_counter = Signal(log2_int(reset_cycles), reset=reset_cycles - 1) ic_reset = Signal(reset=1) sync = getattr(self.sync, cd.name) sync += \ @@ -385,8 +385,8 @@ class USMMCM(XilinxClocking): class USIDELAYCTRL(Module): - def __init__(self, cd): - reset_counter = Signal(6, reset=63) + def __init__(self, cd, reset_cycles=64): + reset_counter = Signal(log2_int(reset_cycles), reset=reset_cycles - 1) ic_reset = Signal(reset=1) sync = getattr(self.sync, cd.name) sync += \ -- 2.30.2