From ae5ca451dc8159b5756fd159f17cb97dc590285a Mon Sep 17 00:00:00 2001 From: Michael Nolan Date: Mon, 9 Mar 2020 10:54:02 -0400 Subject: [PATCH] Migrate imports to use absolute imports --- src/soc/decoder/power_decoder.py | 9 +++++---- src/soc/decoder/power_decoder2.py | 7 ++++--- src/soc/decoder/power_fields.py | 2 +- src/soc/decoder/power_fieldsn.py | 2 +- 4 files changed, 11 insertions(+), 9 deletions(-) diff --git a/src/soc/decoder/power_decoder.py b/src/soc/decoder/power_decoder.py index 5b5e7103..eb7c80a6 100644 --- a/src/soc/decoder/power_decoder.py +++ b/src/soc/decoder/power_decoder.py @@ -55,12 +55,13 @@ Top Level: from nmigen import Module, Elaboratable, Signal from nmigen.cli import rtlil -from power_enums import (Function, Form, InternalOp, In1Sel, In2Sel, In3Sel, - OutSel, RC, LdstLen, CryIn, get_csv, single_bit_flags, +from soc.decoder.power_enums import (Function, Form, InternalOp, + In1Sel, In2Sel, In3Sel, OutSel, RC, LdstLen, + CryIn, get_csv, single_bit_flags, get_signal_name, default_values) from collections import namedtuple -from power_fields import DecodeFields -from power_fieldsn import SigDecode, SignalBitRange +from soc.decoder.power_fields import DecodeFields +from soc.decoder.power_fieldsn import SigDecode, SignalBitRange Subdecoder = namedtuple("Subdecoder", ["pattern", "opcodes", "opint", "bitsel", "suffix", "subdecoders"]) diff --git a/src/soc/decoder/power_decoder2.py b/src/soc/decoder/power_decoder2.py index 1b7435a0..81805a73 100644 --- a/src/soc/decoder/power_decoder2.py +++ b/src/soc/decoder/power_decoder2.py @@ -6,9 +6,10 @@ based on Anton Blanchard microwatt decode2.vhdl from nmigen import Module, Elaboratable, Signal, Mux, Const from nmigen.cli import rtlil -from power_decoder import create_pdecode -from power_enums import (InternalOp, CryIn, Function, LdstLen, - In1Sel, In2Sel, In3Sel, OutSel, SPR, RC) +from soc.decoder.power_decoder import create_pdecode +from soc.decoder.power_enums import (InternalOp, CryIn, Function, + LdstLen, In1Sel, In2Sel, In3Sel, + OutSel, SPR, RC) class DecodeA(Elaboratable): diff --git a/src/soc/decoder/power_fields.py b/src/soc/decoder/power_fields.py index a6352206..aabf591a 100644 --- a/src/soc/decoder/power_fields.py +++ b/src/soc/decoder/power_fields.py @@ -1,5 +1,5 @@ from collections import OrderedDict, namedtuple -from power_enums import download_wiki_file +from soc.decoder.power_enums import download_wiki_file class BitRange(OrderedDict): diff --git a/src/soc/decoder/power_fieldsn.py b/src/soc/decoder/power_fieldsn.py index e603bbd3..a5e03a11 100644 --- a/src/soc/decoder/power_fieldsn.py +++ b/src/soc/decoder/power_fieldsn.py @@ -1,5 +1,5 @@ from collections import OrderedDict -from power_fields import DecodeFields, BitRange +from soc.decoder.power_fields import DecodeFields, BitRange from nmigen import Module, Elaboratable, Signal, Cat from nmigen.cli import rtlil -- 2.30.2