From ae6ef923afc0e9832acae88492b748c601755049 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Sat, 21 Mar 2020 18:26:58 +0100 Subject: [PATCH] targets: fix typos in previous changes. --- litex/boards/targets/kcu105.py | 2 +- litex/boards/targets/netv2.py | 2 +- litex/boards/targets/nexys4ddr.py | 4 ++-- litex/boards/targets/ulx3s.py | 2 +- litex/boards/targets/versa_ecp5.py | 6 +++--- 5 files changed, 8 insertions(+), 8 deletions(-) diff --git a/litex/boards/targets/kcu105.py b/litex/boards/targets/kcu105.py index cd9beb19..30ff747e 100755 --- a/litex/boards/targets/kcu105.py +++ b/litex/boards/targets/kcu105.py @@ -54,7 +54,7 @@ class BaseSoC(SoCCore): platform = kcu105.Platform() # SoCCore ---------------------------------------------------------------------------------- - SoCCore.__init__(self, platform, clk_freq=sys_clk_freq, with_ethernet=False, **kwargs) + SoCCore.__init__(self, platform, clk_freq=sys_clk_freq, **kwargs) # CRG -------------------------------------------------------------------------------------- self.submodules.crg = _CRG(platform, sys_clk_freq) diff --git a/litex/boards/targets/netv2.py b/litex/boards/targets/netv2.py index f163ae7d..3bb14c56 100755 --- a/litex/boards/targets/netv2.py +++ b/litex/boards/targets/netv2.py @@ -49,7 +49,7 @@ class BaseSoC(SoCCore): def __init__(self, sys_clk_freq=int(100e6), with_ethernet=False, **kwargs): platform = netv2.Platform() - # SoCCore --------------------------------------------------------------------------------- + # SoCCore ---------------------------------------------------------------------------------- SoCCore.__init__(self, platform, clk_freq=sys_clk_freq, **kwargs) # CRG -------------------------------------------------------------------------------------- diff --git a/litex/boards/targets/nexys4ddr.py b/litex/boards/targets/nexys4ddr.py index ba0d6c1d..a4b617df 100755 --- a/litex/boards/targets/nexys4ddr.py +++ b/litex/boards/targets/nexys4ddr.py @@ -54,8 +54,8 @@ class BaseSoC(SoCCore): def __init__(self, sys_clk_freq=int(75e6), with_ethernet=False, **kwargs): platform = nexys4ddr.Platform() - # SoCSDRAM --------------------------------------------------------------------------------- - SoCSDRAM.__init__(self, platform, clk_freq=sys_clk_freq, **kwargs) + # SoCCore ----------------------------------_----------------------------------------------- + SoCCore.__init__(self, platform, clk_freq=sys_clk_freq, **kwargs) # CRG -------------------------------------------------------------------------------------- self.submodules.crg = _CRG(platform, sys_clk_freq) diff --git a/litex/boards/targets/ulx3s.py b/litex/boards/targets/ulx3s.py index ce0ddcdb..17b30a52 100755 --- a/litex/boards/targets/ulx3s.py +++ b/litex/boards/targets/ulx3s.py @@ -10,7 +10,7 @@ import sys from migen import * from migen.genlib.resetsync import AsyncResetSynchronizer -from litex_boards.platforms import ulx3s +from litex.boards.platforms import ulx3s from litex.build.lattice.trellis import trellis_args, trellis_argdict diff --git a/litex/boards/targets/versa_ecp5.py b/litex/boards/targets/versa_ecp5.py index 21181b11..0669e274 100755 --- a/litex/boards/targets/versa_ecp5.py +++ b/litex/boards/targets/versa_ecp5.py @@ -71,12 +71,12 @@ class _CRG(Module): # BaseSoC ------------------------------------------------------------------------------------------ -class BaseSoC(SoCSDRAM): +class BaseSoC(SoCCore): def __init__(self, sys_clk_freq=int(75e6), with_ethernet=False, toolchain="trellis", **kwargs): platform = versa_ecp5.Platform(toolchain=toolchain) - # SoCSDRAM --------------------------------------------------------------------------------- - SoCSDRAM.__init__(self, platform, clk_freq=sys_clk_freq, **kwargs) + # SoCCore -----------------------------------------_---------------------------------------- + SoCCore.__init__(self, platform, clk_freq=sys_clk_freq, **kwargs) # CRG -------------------------------------------------------------------------------------- self.submodules.crg = _CRG(platform, sys_clk_freq) -- 2.30.2