From ae75e7fc45850663b1c2e3e8b22b00ae4d24b168 Mon Sep 17 00:00:00 2001 From: Ian Jiang Date: Fri, 31 Jul 2020 16:00:05 +0800 Subject: [PATCH] arch-riscv: Fix disassembling of float register instructions In disassembling of float register instructions, Gem5 always gives 2 source registers rs1 and rs2. However, this is not correct for Mul-Add instructions which have three rs1, rs2, and rs3, and for Move, Convert instructions which have only rs1. For example: (Gem5 output vs Expected) - fmadd.d fa0,fa0,fa4 vs fmadd.d fa0,fa0,fa4,fa5 - fcvt.d.l fa4,a6,zero vs fcvt.d.l fa4,a6 This patch fixes the problem. Change-Id: I02d840eab602ac4a9782911b3cdff2935dfe5e68 Signed-off-by: Ian Jiang Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/32054 Reviewed-by: Jason Lowe-Power Maintainer: Jason Lowe-Power Tested-by: kokoro --- src/arch/riscv/insts/standard.cc | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/src/arch/riscv/insts/standard.cc b/src/arch/riscv/insts/standard.cc index bb621ae7a..e6c2b67ae 100644 --- a/src/arch/riscv/insts/standard.cc +++ b/src/arch/riscv/insts/standard.cc @@ -47,8 +47,11 @@ RegOp::generateDisassembly(Addr pc, const Loader::SymbolTable *symtab) const { stringstream ss; ss << mnemonic << ' ' << registerName(_destRegIdx[0]) << ", " << - registerName(_srcRegIdx[0]) << ", " << - registerName(_srcRegIdx[1]); + registerName(_srcRegIdx[0]); + if (_srcRegIdx[1].index() != 0) + ss << ", " << registerName(_srcRegIdx[1]); + if (_srcRegIdx[2].index() != 0) + ss << ", " << registerName(_srcRegIdx[2]); return ss.str(); } -- 2.30.2