From ae970875a78bdb373b573c9143f3815dce55b20f Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Sat, 27 Feb 2021 12:38:15 +0000 Subject: [PATCH] add corresponding VL=0 unit test as from 161b7d67b in svp64_cases.py --- src/soc/decoder/isa/test_caller_svp64.py | 26 ++++++++++++++++++++++++ 1 file changed, 26 insertions(+) diff --git a/src/soc/decoder/isa/test_caller_svp64.py b/src/soc/decoder/isa/test_caller_svp64.py index 388b7df9..14a72d26 100644 --- a/src/soc/decoder/isa/test_caller_svp64.py +++ b/src/soc/decoder/isa/test_caller_svp64.py @@ -107,6 +107,32 @@ class DecoderTestCase(FHDLTestCase): sim = self.run_tst_program(program, initial_regs, svstate) self._check_regs(sim, expected_regs) + def test_sv_add_vl_0(self): + # adds: + # none because VL is zer0 + isa = SVP64Asm(['sv.add 1, 5.v, 9.v' + ]) + lst = list(isa) + print ("listing", lst) + + # initial values in GPR regfile + initial_regs = [0] * 32 + initial_regs[9] = 0x1234 + initial_regs[10] = 0x1111 + initial_regs[5] = 0x4321 + initial_regs[6] = 0x2223 + # SVSTATE (in this case, VL=0) + svstate = SVP64State() + svstate.vl[0:7] = 0 # VL + svstate.maxvl[0:7] = 0 # MAXVL + print ("SVSTATE", bin(svstate.spr.asint())) + # copy before running + expected_regs = deepcopy(initial_regs) + + with Program(lst, bigendian=False) as program: + sim = self.run_tst_program(program, initial_regs, svstate) + self._check_regs(sim, expected_regs) + def test_sv_add_cr(self): # adds when Rc=1: TODO CRs higher up # 1 = 5 + 9 => 0 = -1+1 CR0=0b100 -- 2.30.2