From aeb15398182abf5de7e340976e204195ab80a739 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Wed, 25 Sep 2019 17:22:30 -0700 Subject: [PATCH] Rework xilinx_dsp postAdd for new wreduce call --- passes/pmgen/xilinx_dsp.pmg | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/passes/pmgen/xilinx_dsp.pmg b/passes/pmgen/xilinx_dsp.pmg index bca44c08d..e256f7d7e 100644 --- a/passes/pmgen/xilinx_dsp.pmg +++ b/passes/pmgen/xilinx_dsp.pmg @@ -271,9 +271,9 @@ match postAdd filter !ffMcemux || nusers(port(postAdd, AB)) == 3 index port(postAdd, AB)[0] === sigP[0] - filter GetSize(port(postAdd, AB)) <= GetSize(sigP) - filter port(postAdd, AB) == sigP.extract(0, GetSize(port(postAdd, AB))) - filter nusers(sigP.extract_end(GetSize(port(postAdd, AB)))) <= 1 + filter GetSize(port(postAdd, AB)) >= GetSize(sigP) + filter port(postAdd, AB).extract(0, GetSize(sigP)) == sigP + filter port(postAdd, AB).extract_end(GetSize(sigP)) == SigSpec(sigP[GetSize(sigP)-1], GetSize(port(postAdd, AB))-GetSize(sigP)) set postAddAB AB optional endmatch -- 2.30.2