From aebbfffd71ab6a85f86ef44f40b1d46a7d6a60ee Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Fri, 27 Sep 2019 11:57:53 -0700 Subject: [PATCH] Ooops AREG and BREG to default to -1 --- passes/pmgen/xilinx_dsp_cascade.pmg | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/passes/pmgen/xilinx_dsp_cascade.pmg b/passes/pmgen/xilinx_dsp_cascade.pmg index 714316808..6f4ac5849 100644 --- a/passes/pmgen/xilinx_dsp_cascade.pmg +++ b/passes/pmgen/xilinx_dsp_cascade.pmg @@ -146,7 +146,7 @@ code next endcode code argQ clock AREG - AREG = 0; + AREG = -1; if (next) { Cell *prev = std::get<0>(chain.back()); if (param(prev, \AREG, 2).as_int() > 0 && @@ -175,7 +175,7 @@ reject_AREG: ; endcode code argQ clock BREG - BREG = 0; + BREG = -1; if (next) { Cell *prev = std::get<0>(chain.back()); if (param(prev, \BREG, 2).as_int() > 0 && -- 2.30.2