From aeea9fb1c80668de6057fa919b6eeb4bf4790a51 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Mon, 6 Jul 2020 23:15:55 +0100 Subject: [PATCH] add mul unit to test_issuer --- src/soc/simple/issuer.py | 1 + 1 file changed, 1 insertion(+) diff --git a/src/soc/simple/issuer.py b/src/soc/simple/issuer.py index 9feafaf1..e787df5f 100644 --- a/src/soc/simple/issuer.py +++ b/src/soc/simple/issuer.py @@ -163,6 +163,7 @@ class TestIssuer(Elaboratable): if __name__ == '__main__': units = {'alu': 1, 'cr': 1, 'branch': 1, 'trap': 1, 'logical': 1, 'spr': 1, + 'mul': 1, 'shiftrot': 1} pspec = TestMemPspec(ldst_ifacetype='bare_wb', imem_ifacetype='bare_wb', -- 2.30.2