From aef234441eda34cb657f52f12fc03a0622bc8c55 Mon Sep 17 00:00:00 2001 From: lkcl Date: Sun, 12 Jun 2022 13:24:30 +0100 Subject: [PATCH] --- openpower/sv/compliancy_levels.mdwn | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-) diff --git a/openpower/sv/compliancy_levels.mdwn b/openpower/sv/compliancy_levels.mdwn index 0c2424731..9788231f6 100644 --- a/openpower/sv/compliancy_levels.mdwn +++ b/openpower/sv/compliancy_levels.mdwn @@ -39,6 +39,7 @@ Summary of Compliancy Levels, each Level includes all lower levels: overrides, and Saturation and Mapreduce/Iteration Modes. * **3D/Advanced/Supercomputing**: all SV Branch instructions; crweird and vector-assist instructions (`set-before-first` etc); + Swizzle Move instructions; Matrix, DCT/FFT and Indexing REMAP capability; Fail-First and Predicate-Result Modes. @@ -138,8 +139,13 @@ This Compliancy Level is for highest performance and energy efficiency. All aspects of SVP64 must be entirely implemented, in full, in Hardware. How that is achieved is entirely at the discretion of the implementor: there are no hard requirements of any kind on the level of performance, -just as there are none in the Vulkan(TM) Specification. Throughout the SV +just as there are none in the Vulkan(TM) Specification. + +Throughout the SV Specification however there are hints to Micro-Architects: byte-level write-enable lines on Register Files is strongly recommended, for -example. +example, in order to avoid unnecessary Read-Modify-Write cycles and +additional Register Hazard Dependencies on fine-grained (8/16/32-bit) +operations. Just as with SRAMs multiple write-enable lines may be +raised to update higher-width elements. -- 2.30.2