From af129d07878665c2c11a6801063f007317114389 Mon Sep 17 00:00:00 2001
From: Jiong Wang <jiong.wang@arm.com>
Date: Mon, 19 Jan 2015 14:13:33 +0000
Subject: [PATCH] [AArch64] Remove ashift pattern for QI/HI

2015-01-19  Jiong Wang  <jiong.wang@arm.com>
	    Andrew Pinski  <apinski@cavium.com>

  gcc/
    PR target/64304
    * config/aarch64/aarch64.md (define_insn "*ashl<mode>3_insn"): Deleted.
    (ashl<mode>3): Don't expand if operands[2] is not constant.

  gcc/testsuite/
    * gcc.target/aarch64/pr64304.c: New testcase.


Co-Authored-By: Andrew Pinski <apinski@cavium.com>

From-SVN: r219844
---
 gcc/ChangeLog                              |  7 +++++++
 gcc/config/aarch64/aarch64.md              | 11 ++---------
 gcc/testsuite/ChangeLog                    |  4 ++++
 gcc/testsuite/gcc.target/aarch64/pr64304.c | 18 ++++++++++++++++++
 4 files changed, 31 insertions(+), 9 deletions(-)
 create mode 100644 gcc/testsuite/gcc.target/aarch64/pr64304.c

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 605b87e9070..4e03d90c1b5 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,10 @@
+2015-01-19  Jiong Wang  <jiong.wang@arm.com>
+	    Andrew Pinski  <apinski@cavium.com>
+
+	PR target/64304
+	* config/aarch64/aarch64.md (define_insn "*ashl<mode>3_insn"): Deleted.
+	(ashl<mode>3): Don't expand if operands[2] is not constant.
+
 2015-01-19  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
 
 	PR target/64448
diff --git a/gcc/config/aarch64/aarch64.md b/gcc/config/aarch64/aarch64.md
index fde5e4f0223..bc49fbe68a9 100644
--- a/gcc/config/aarch64/aarch64.md
+++ b/gcc/config/aarch64/aarch64.md
@@ -3283,6 +3283,8 @@
 	    DONE;
           }
       }
+    else
+      FAIL;
   }
 )
 
@@ -3507,15 +3509,6 @@
   [(set_attr "type" "shift_reg")]
 )
 
-(define_insn "*ashl<mode>3_insn"
-  [(set (match_operand:SHORT 0 "register_operand" "=r")
-	(ashift:SHORT (match_operand:SHORT 1 "register_operand" "r")
-		      (match_operand:QI 2 "aarch64_reg_or_shift_imm_si" "rUss")))]
-  ""
-  "lsl\\t%<w>0, %<w>1, %<w>2"
-  [(set_attr "type" "shift_reg")]
-)
-
 (define_insn "*<optab><mode>3_insn"
   [(set (match_operand:SHORT 0 "register_operand" "=r")
 	(ASHIFT:SHORT (match_operand:SHORT 1 "register_operand" "r")
diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index 87017f73e12..7e1bcc42a8f 100644
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,3 +1,7 @@
+2015-01-19  Jiong Wang  <jiong.wang@arm.com>
+
+	* gcc.target/aarch64/pr64304.c: New testcase.
+
 2014-01-19  Igor Zamyatin  <igor.zamyatin@intel.com>
 
 	PR rtl-optimization/64081
diff --git a/gcc/testsuite/gcc.target/aarch64/pr64304.c b/gcc/testsuite/gcc.target/aarch64/pr64304.c
new file mode 100644
index 00000000000..5423bb3e0ca
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/pr64304.c
@@ -0,0 +1,18 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 --save-temps" } */
+
+unsigned char byte = 0;
+
+void
+set_bit (unsigned int bit, unsigned char value)
+{
+  unsigned char mask = (unsigned char) (1 << (bit & 7));
+
+  if (! value)
+    byte &= (unsigned char)~mask;
+  else
+    byte |= mask;
+  /* { dg-final { scan-assembler "and\tw\[0-9\]+, w\[0-9\]+, 7" } } */
+}
+
+/* { dg-final { cleanup-saved-temps } } */
-- 
2.30.2