From af17e392b2e50c86dd9a11ee72ce119a4b0033a5 Mon Sep 17 00:00:00 2001
From: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Date: Thu, 7 May 2020 12:05:23 +0300
Subject: [PATCH] genxml: run sorting script

Helps running diff/meld between generations :)

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4938>
---
 src/intel/genxml/gen11.xml | 16 ++++++++--------
 src/intel/genxml/gen12.xml | 34 +++++++++++++++++-----------------
 2 files changed, 25 insertions(+), 25 deletions(-)

diff --git a/src/intel/genxml/gen11.xml b/src/intel/genxml/gen11.xml
index 6d5ba940cda..06e90f23135 100644
--- a/src/intel/genxml/gen11.xml
+++ b/src/intel/genxml/gen11.xml
@@ -6233,11 +6233,11 @@
 
   <instruction name="PIPE_CONTROL" bias="2" length="6" engine="render">
     <field name="DWord Length" start="0" end="7" type="uint" default="4"/>
+    <field name="HDC Pipeline Flush Enable" start="9" end="9" type="bool"/>
     <field name="3D Command Sub Opcode" start="16" end="23" type="uint" default="0"/>
     <field name="3D Command Opcode" start="24" end="26" type="uint" default="2"/>
     <field name="Command SubType" start="27" end="28" type="uint" default="3"/>
     <field name="Command Type" start="29" end="31" type="uint" default="3"/>
-    <field name="HDC Pipeline Flush Enable" start="9" end="9" type="bool"/>
     <field name="Depth Cache Flush Enable" start="32" end="32" type="bool"/>
     <field name="Stall At Pixel Scoreboard" start="33" end="33" type="bool"/>
     <field name="State Cache Invalidation Enable" start="34" end="34" type="bool"/>
@@ -7005,13 +7005,6 @@
     <field name="All Allocation" start="25" end="31" type="uint"/>
   </register>
 
-  <register name="TCCNTLREG" length="1" num="0xb0a4">
-    <field name="URB Partial Write Merging Enable" start="0" end="0" type="bool"/>
-    <field name="Color/Z Partial Write Merging Enable" start="1" end="1" type="bool"/>
-    <field name="L3 Data Partial Write Merging Enable" start="2" end="2" type="bool"/>
-    <field name="TC Disable" start="3" end="3" type="bool"/>
-  </register>
-
   <register name="PERFCNT1" length="2" num="0x91b8">
     <field name="Value" start="0" end="43" type="uint"/>
     <field name="Event Selection" start="52" end="59" type="uint"/>
@@ -7165,6 +7158,13 @@
     <field name="Write Offset" start="2" end="31" type="offset"/>
   </register>
 
+  <register name="TCCNTLREG" length="1" num="0xb0a4">
+    <field name="URB Partial Write Merging Enable" start="0" end="0" type="bool"/>
+    <field name="Color/Z Partial Write Merging Enable" start="1" end="1" type="bool"/>
+    <field name="L3 Data Partial Write Merging Enable" start="2" end="2" type="bool"/>
+    <field name="TC Disable" start="3" end="3" type="bool"/>
+  </register>
+
   <register name="VCS_INSTDONE" length="1" num="0x1206c">
     <field name="Ring Enable" start="0" end="0" type="bool"/>
     <field name="USB Done" start="1" end="1" type="bool"/>
diff --git a/src/intel/genxml/gen12.xml b/src/intel/genxml/gen12.xml
index 3eebc30f4be..38fb8a1e904 100644
--- a/src/intel/genxml/gen12.xml
+++ b/src/intel/genxml/gen12.xml
@@ -249,6 +249,17 @@
     </group>
   </struct>
 
+  <struct name="3DSTATE_SO_BUFFER_INDEX_BODY" length="7">
+    <field name="Stream Output Buffer Offset Address Enable" start="20" end="20" type="bool"/>
+    <field name="Stream Offset Write Enable" start="21" end="21" type="bool"/>
+    <field name="MOCS" start="22" end="28" type="uint"/>
+    <field name="SO Buffer Enable" start="31" end="31" type="bool"/>
+    <field name="Surface Base Address" start="34" end="79" type="address"/>
+    <field name="Surface Size" start="96" end="125" type="uint"/>
+    <field name="Stream Output Buffer Offset Address" start="130" end="175" type="address"/>
+    <field name="Stream Offset" start="192" end="223" type="uint"/>
+  </struct>
+
   <struct name="BINDING_TABLE_EDIT_ENTRY" length="1">
     <field name="Surface State Pointer" start="0" end="15" type="offset"/>
     <field name="Binding Table Index" start="16" end="23" type="uint"/>
@@ -1230,17 +1241,6 @@
     <field name="Component 0 Control" start="60" end="62" type="3D_Vertex_Component_Control"/>
   </struct>
 
-  <struct name="3DSTATE_SO_BUFFER_INDEX_BODY" length="7">
-    <field name="Stream Output Buffer Offset Address Enable" start="20" end="20" type="bool"/>
-    <field name="Stream Offset Write Enable" start="21" end="21" type="bool"/>
-    <field name="MOCS" start="22" end="28" type="uint"/>
-    <field name="SO Buffer Enable" start="31" end="31" type="bool"/>
-    <field name="Surface Base Address" start="34" end="79" type="address"/>
-    <field name="Surface Size" start="96" end="125" type="uint"/>
-    <field name="Stream Output Buffer Offset Address" start="130" end="175" type="address"/>
-    <field name="Stream Offset" start="192" end="223" type="uint"/>
-  </struct>
-
   <instruction name="3DPRIMITIVE" bias="2" length="7" engine="render">
     <field name="DWord Length" start="0" end="7" type="uint" default="5"/>
     <field name="Predicate Enable" start="8" end="8" type="bool"/>
@@ -6373,11 +6373,11 @@
 
   <instruction name="PIPE_CONTROL" bias="2" length="6" engine="render">
     <field name="DWord Length" start="0" end="7" type="uint" default="4"/>
+    <field name="HDC Pipeline Flush Enable" start="9" end="9" type="bool"/>
     <field name="3D Command Sub Opcode" start="16" end="23" type="uint" default="0"/>
     <field name="3D Command Opcode" start="24" end="26" type="uint" default="2"/>
     <field name="Command SubType" start="27" end="28" type="uint" default="3"/>
     <field name="Command Type" start="29" end="31" type="uint" default="3"/>
-    <field name="HDC Pipeline Flush Enable" start="9" end="9" type="bool"/>
     <field name="Depth Cache Flush Enable" start="32" end="32" type="bool"/>
     <field name="Stall At Pixel Scoreboard" start="33" end="33" type="bool"/>
     <field name="State Cache Invalidation Enable" start="34" end="34" type="bool"/>
@@ -7055,11 +7055,6 @@
     <field name="HIZ Plane Optimization disable bit Mask" start="25" end="25" type="bool"/>
   </register>
 
-  <register name="HIZ_CHICKEN" length="1" num="0x7018">
-    <field name="HZ Depth Test LE/GE Optimization Disable" start="13" end="13" type="bool"/>
-    <field name="HZ Depth Test LE/GE Optimization Disable Mask" start="29" end="29" type="bool"/>
-  </register>
-
   <register name="COMMON_SLICE_CHICKEN3" length="1" num="0x7304">
     <field name="PS Thread Panic Dispatch" start="6" end="7" type="uint"/>
     <field name="PS Thread Panic Dispatch Mask" start="22" end="23" type="uint"/>
@@ -7116,6 +7111,11 @@
     <field name="Enabled Texel Offset Precision Fix Mask" start="17" end="17" type="bool"/>
   </register>
 
+  <register name="HIZ_CHICKEN" length="1" num="0x7018">
+    <field name="HZ Depth Test LE/GE Optimization Disable" start="13" end="13" type="bool"/>
+    <field name="HZ Depth Test LE/GE Optimization Disable Mask" start="29" end="29" type="bool"/>
+  </register>
+
   <register name="HS_INVOCATION_COUNT" length="2" num="0x2300">
     <field name="HS Invocation Count Report" start="0" end="63" type="uint"/>
   </register>
-- 
2.30.2