From af1f3b35b0259d705830cc624a43e7936e137d1c Mon Sep 17 00:00:00 2001 From: Timothy Hayes Date: Tue, 21 Apr 2020 10:26:02 +0100 Subject: [PATCH] mem-ruby: fix MESI_Three_Level erroneous transition The MESI_Three_Level protocol includes a transition in its L1 definition to invalidate an SM state but this transition does not notify the L0 cache. The unintended side effect of this allows stale values to be read by the L0 cache. This can cause incorrect behaviour when executing LL/SC based mutexes. This patch ensures that all invalidates to SM states are exposed to the L0 cache. Change-Id: I7fefabdaa8027fdfa4c9c362abd7e467493196aa Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/28047 Reviewed-by: John Alsop Reviewed-by: Pouya Fotouhi Maintainer: Bobby R. Bruce Tested-by: kokoro --- src/mem/ruby/protocol/MESI_Three_Level-L1cache.sm | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/src/mem/ruby/protocol/MESI_Three_Level-L1cache.sm b/src/mem/ruby/protocol/MESI_Three_Level-L1cache.sm index 00d897a81..1890bcc57 100644 --- a/src/mem/ruby/protocol/MESI_Three_Level-L1cache.sm +++ b/src/mem/ruby/protocol/MESI_Three_Level-L1cache.sm @@ -262,7 +262,8 @@ machine(MachineType:L1Cache, "MESI Directory L1 Cache CMP") } bool inL0Cache(State state) { - if (state == State:S || state == State:E || state == State:M || + if (state == State:S || state == State:E || + state == State:M || state == State:SM || state == State:S_IL0 || state == State:E_IL0 || state == State:M_IL0 || state == State:SM_IL0) { return true; @@ -996,7 +997,7 @@ machine(MachineType:L1Cache, "MESI Directory L1 Cache CMP") } // Transitions from IM - transition({IM,SM}, Inv, IM) { + transition(IM, Inv, IM) { fi_sendInvAck; l_popL2RequestQueue; } -- 2.30.2