From af48075062e32c2fd7816af4096d97459c5e5fc2 Mon Sep 17 00:00:00 2001 From: David Malcolm Date: Wed, 27 Aug 2014 19:12:31 +0000 Subject: [PATCH] mn10300: Fixes to PARALLEL handling within mn10300_adjust_sched_cost 2014-08-27 David Malcolm * gcc/config/mn10300/mn10300.c (is_load_insn): Rename to... (set_is_load_p): ...this, updating to work on a SET pattern rather than an insn. (is_store_insn): Rename to... (set_is_store_p): ...this, updating to work on a SET pattern rather than an insn. (mn10300_adjust_sched_cost): Move call to get_attr_timings from top of function to where it is needed. Rewrite the bogus condition that checks for "insn" and "dep" being PARALLEL to instead use single_set, introducing locals "insn_set" and "dep_set". Given that we only ever returned "cost" for a non-pair of SETs, bail out early if we don't have a pair of SET. Rewrite all uses of PATTERN (dep) and PATTERN (insn) to instead use the new locals "insn_set" and "dep_set", and update calls to is_load_insn and is_store_insn to be calls to set_is_load_p and set_is_store_p. From-SVN: r214582 --- gcc/ChangeLog | 19 ++++++++++++++ gcc/config/mn10300/mn10300.c | 51 ++++++++++++++++-------------------- 2 files changed, 42 insertions(+), 28 deletions(-) diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 66eece0e809..2689e2db19c 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,22 @@ +2014-08-27 David Malcolm + + * gcc/config/mn10300/mn10300.c (is_load_insn): Rename to... + (set_is_load_p): ...this, updating to work on a SET pattern rather + than an insn. + (is_store_insn): Rename to... + (set_is_store_p): ...this, updating to work on a SET pattern + rather than an insn. + (mn10300_adjust_sched_cost): Move call to get_attr_timings from + top of function to where it is needed. Rewrite the bogus + condition that checks for "insn" and "dep" being PARALLEL to + instead use single_set, introducing locals "insn_set" and + "dep_set". Given that we only ever returned "cost" for a non-pair + of SETs, bail out early if we don't have a pair of SET. + Rewrite all uses of PATTERN (dep) and PATTERN (insn) to instead + use the new locals "insn_set" and "dep_set", and update calls to + is_load_insn and is_store_insn to be calls to set_is_load_p and + set_is_store_p. + 2014-08-27 Guozhi Wei PR target/62262 diff --git a/gcc/config/mn10300/mn10300.c b/gcc/config/mn10300/mn10300.c index d229ca9638b..ca79f6d16ac 100644 --- a/gcc/config/mn10300/mn10300.c +++ b/gcc/config/mn10300/mn10300.c @@ -2742,21 +2742,15 @@ mn10300_select_cc_mode (enum rtx_code code, rtx x, rtx y ATTRIBUTE_UNUSED) } static inline bool -is_load_insn (rtx insn) +set_is_load_p (rtx set) { - if (GET_CODE (PATTERN (insn)) != SET) - return false; - - return MEM_P (SET_SRC (PATTERN (insn))); + return MEM_P (SET_SRC (set)); } static inline bool -is_store_insn (rtx insn) +set_is_store_p (rtx set) { - if (GET_CODE (PATTERN (insn)) != SET) - return false; - - return MEM_P (SET_DEST (PATTERN (insn))); + return MEM_P (SET_DEST (set)); } /* Update scheduling costs for situations that cannot be @@ -2768,33 +2762,36 @@ is_store_insn (rtx insn) static int mn10300_adjust_sched_cost (rtx insn, rtx link, rtx dep, int cost) { - int timings = get_attr_timings (insn); + rtx insn_set; + rtx dep_set; + int timings; if (!TARGET_AM33) return 1; - if (GET_CODE (insn) == PARALLEL) - insn = XVECEXP (insn, 0, 0); + /* We are only interested in pairs of SET. */ + insn_set = single_set (insn); + if (!insn_set) + return cost; - if (GET_CODE (dep) == PARALLEL) - dep = XVECEXP (dep, 0, 0); + dep_set = single_set (dep); + if (!dep_set) + return cost; /* For the AM34 a load instruction that follows a store instruction incurs an extra cycle of delay. */ if (mn10300_tune_cpu == PROCESSOR_AM34 - && is_load_insn (dep) - && is_store_insn (insn)) + && set_is_load_p (dep_set) + && set_is_store_p (insn_set)) cost += 1; /* For the AM34 a non-store, non-branch FPU insn that follows another FPU insn incurs a one cycle throughput increase. */ else if (mn10300_tune_cpu == PROCESSOR_AM34 - && ! is_store_insn (insn) + && ! set_is_store_p (insn_set) && ! JUMP_P (insn) - && GET_CODE (PATTERN (dep)) == SET - && GET_CODE (PATTERN (insn)) == SET - && GET_MODE_CLASS (GET_MODE (SET_SRC (PATTERN (dep)))) == MODE_FLOAT - && GET_MODE_CLASS (GET_MODE (SET_SRC (PATTERN (insn)))) == MODE_FLOAT) + && GET_MODE_CLASS (GET_MODE (SET_SRC (dep_set))) == MODE_FLOAT + && GET_MODE_CLASS (GET_MODE (SET_SRC (insn_set))) == MODE_FLOAT) cost += 1; /* Resolve the conflict described in section 1-7-4 of @@ -2816,23 +2813,21 @@ mn10300_adjust_sched_cost (rtx insn, rtx link, rtx dep, int cost) return cost; /* Check that the instruction about to scheduled is an FPU instruction. */ - if (GET_CODE (PATTERN (dep)) != SET) - return cost; - - if (GET_MODE_CLASS (GET_MODE (SET_SRC (PATTERN (dep)))) != MODE_FLOAT) + if (GET_MODE_CLASS (GET_MODE (SET_SRC (dep_set))) != MODE_FLOAT) return cost; /* Now check to see if the previous instruction is a load or store. */ - if (! is_load_insn (insn) && ! is_store_insn (insn)) + if (! set_is_load_p (insn_set) && ! set_is_store_p (insn_set)) return cost; /* XXX: Verify: The text of 1-7-4 implies that the restriction only applies when an INTEGER load/store precedes an FPU instruction, but is this true ? For now we assume that it is. */ - if (GET_MODE_CLASS (GET_MODE (SET_SRC (PATTERN (insn)))) != MODE_INT) + if (GET_MODE_CLASS (GET_MODE (SET_SRC (insn_set))) != MODE_INT) return cost; /* Extract the latency value from the timings attribute. */ + timings = get_attr_timings (insn); return timings < 100 ? (timings % 10) : (timings % 100); } -- 2.30.2