From af52842fbb250d795d110d79fd2ac91442ad98b9 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Tue, 12 Feb 2019 12:12:40 +0100 Subject: [PATCH] soc_sdram: add use_full_memory_we parameter to allow disabling vivado workaround on small l2 caches --- litex/soc/integration/soc_sdram.py | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/litex/soc/integration/soc_sdram.py b/litex/soc/integration/soc_sdram.py index 4e819139..64b218ad 100644 --- a/litex/soc/integration/soc_sdram.py +++ b/litex/soc/integration/soc_sdram.py @@ -55,7 +55,7 @@ class SoCSDRAM(SoCCore): raise FinalizeError self._wb_sdram_ifs.append(interface) - def register_sdram(self, phy, geom_settings, timing_settings, use_axi=False, **kwargs): + def register_sdram(self, phy, geom_settings, timing_settings, use_axi=False, use_full_memory_we=True, **kwargs): assert not self._sdram_phy self._sdram_phy.append(phy) # encapsulate in list to prevent CSR scanning @@ -85,7 +85,7 @@ class SoCSDRAM(SoCCore): # XXX Vivado ->2018.2 workaround, Vivado is not able to map correctly our L2 cache. # Issue is reported to Xilinx, Remove this if ever fixed by Xilinx... from litex.build.xilinx.vivado import XilinxVivadoToolchain - if isinstance(self.platform.toolchain, XilinxVivadoToolchain): + if isinstance(self.platform.toolchain, XilinxVivadoToolchain) and use_full_memory_we: from migen.fhdl.simplify import FullMemoryWE self.submodules.l2_cache = FullMemoryWE()(l2_cache) else: -- 2.30.2