From af65425ca548c7340b492e33316a256db9c36ac4 Mon Sep 17 00:00:00 2001 From: lkcl Date: Wed, 23 Dec 2020 01:19:45 +0000 Subject: [PATCH] --- openpower/sv/vector_ops.mdwn | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/openpower/sv/vector_ops.mdwn b/openpower/sv/vector_ops.mdwn index 7d7acbe48..771632ee8 100644 --- a/openpower/sv/vector_ops.mdwn +++ b/openpower/sv/vector_ops.mdwn @@ -2,8 +2,9 @@ The core OpenPOWER ISA was designed as scalar: SV provides a level of abstraction to add variable-length element-independent parallelism. However, certain classes of instructions only make sense in a Vector context: AVX512 conflictd for example. This section includes such examples. Many of them are from the RISC-V Vector ISA (with thanks to the efforts of RVV's contributors) -However some of these actually could be added to a scalar ISA as bitmanipulation instructions. These are separated out into their own section. +Notes: +* Some of these actually could be added to a scalar ISA as bitmanipulation instructions. These are separated out into their own section. * Instructions suited to 3D GPU workloads (dotproduct, crossproduct, normalise) are out of scope: this document is for more general-purpose instructions that underpin and are critical to general-purpose Vector workloads (including GPU and VPU) * Instructions related to the adaptation of CRs for use as predicate masks are covered separately, by crweird operations. See [[sv/cr_int_predication]]. -- 2.30.2