From af7e2c61335640b4b23bdf907ea9ec94c89c218b Mon Sep 17 00:00:00 2001 From: Samuel Pitoiset Date: Wed, 8 Apr 2020 08:53:47 +0200 Subject: [PATCH] aco: validate 8-bit/16-bit VGPR operands for readfirstlane/readlane/writelane I would expect it to just work as intended and other solutions, like v_and_b32 to make sure the upper bits are 0, might have some overhead. Signed-off-by: Samuel Pitoiset Reviewed-by: Rhys Perry Part-of: --- src/amd/compiler/aco_validate.cpp | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/amd/compiler/aco_validate.cpp b/src/amd/compiler/aco_validate.cpp index e101d20068c..65ca2b45065 100644 --- a/src/amd/compiler/aco_validate.cpp +++ b/src/amd/compiler/aco_validate.cpp @@ -229,7 +229,7 @@ void validate(Program* program, FILE * output) instr->opcode == aco_opcode::v_writelane_b32 || instr->opcode == aco_opcode::v_writelane_b32_e64) { check(!op.isLiteral(), "No literal allowed on VALU instruction", instr.get()); - check(i == 1 || (op.isTemp() && op.regClass() == v1), "Wrong Operand type for VALU instruction", instr.get()); + check(i == 1 || (op.isTemp() && op.regClass().type() == RegType::vgpr && op.bytes() <= 4), "Wrong Operand type for VALU instruction", instr.get()); continue; } if (op.isTemp() && instr->operands[i].regClass().type() == RegType::sgpr) { -- 2.30.2