From af9b7a0ca94afcbe1ab129b5c37f84c15cacebc7 Mon Sep 17 00:00:00 2001 From: lkcl Date: Sun, 4 Jun 2023 12:30:42 +0100 Subject: [PATCH] --- openpower/sv/ls010/trial_addi.mdwn | 59 ++++++++++++++++++++++++++++++ 1 file changed, 59 insertions(+) create mode 100644 openpower/sv/ls010/trial_addi.mdwn diff --git a/openpower/sv/ls010/trial_addi.mdwn b/openpower/sv/ls010/trial_addi.mdwn new file mode 100644 index 000000000..2429f5828 --- /dev/null +++ b/openpower/sv/ls010/trial_addi.mdwn @@ -0,0 +1,59 @@ +# Example demonstration instruction modified to SVP64 (better) + + +Background: + + +**Add Immediate** D-Form + +* addi RT,RA,SI + +``` + DWI: + | 14 | RT | RA | SI | + | 0 | 6 | 11 | 16 31 | +``` + +**Prefixed Add Immediate** MLS:D-form + +* paddi RT,RA,SI,R + +``` + Prefix: + | 1 | 2 | 0 | // | R | // | si0 | + | 0 | 6 | 8 | 9 | 11 | 12 | 14 31 | + + Suffix:: + | 14 | RT | RA | si1 | + | 0 | 6 | 11 | 16 31 | +``` + +**Vectorized Add Immediate** SVP64-RM-1S1D/EXTRA3/Normal:D-form + +* sv.addi RT,RA,SI + +``` + Prefix: : + | 9 | .. | Stuff | EXTRA | MODEBITS | + | 0 | 6 | 8 | 17 26 | 27 31 | + Suffix: + | 14 | RT | RA | SI | + | 0 | 6 | 11 | 16 31 | +``` + +Pseudo-code: + +``` + if "addi" then + RT <- (RA|0) + EXTS64(SI) + if "paddi" & R=0 then + RT <- (RA|0) + EXTS64(si0||si1) + if "paddi" & R=1 then + RT <- CIA + EXTS64(si0||si1) + +``` + +Special Registers Altered: + + None + -- 2.30.2