From afa3ed855f0f1f76b1a428ff15a4ba7ef489c44b Mon Sep 17 00:00:00 2001 From: "David S. Miller" Date: Thu, 26 Apr 2012 08:28:12 +0000 Subject: [PATCH] Fix sparc instruction type settings and sched bugs. gcc/ * config/sparc/sparc.md (attr type): Delete 'fgm_cmp'. (fpack16_vis, fpackfix_vis, fpack32_vis): Set type to fgm_pack. (fmul8x16_vis, fmul8x16au_vis, fmul8x16al_vis, fmul8sux16_vis, fmul8ulx16_vis, fmuld8sux16_vis, fmuld8ulx16_vis): Set type to fgm_mul. (alignaddrsi_vis, alignaddrdi_vis, alignaddrlsi_vis, alignaddrldi_vis): Set type to gsr. (pdist_vis, pdistn_vis): Set type to fgm_pdsit. (fcmp_vis, cmask8_vis, cmask16_vis, cmask32_vis, fchksm16_vis, v3, fmean16_vis, fp64_vis, 3, fucmp8_vis): Set type to fga. * config/sparc/ultra1_2.md: Remove refrences to fgm_cmp. * config/sparc/niagara.md: Likewise. * config/sparc/niagara2.md: Likewise. * config/sparc/ultra3.md: Likewise, and fix type matching for us3_ialuX reservation. From-SVN: r186863 --- gcc/ChangeLog | 21 +++++++++++ gcc/config/sparc/niagara.md | 2 +- gcc/config/sparc/niagara2.md | 4 +-- gcc/config/sparc/sparc.md | 69 ++++++++++++++++++++++-------------- gcc/config/sparc/ultra1_2.md | 4 +-- gcc/config/sparc/ultra3.md | 4 +-- 6 files changed, 70 insertions(+), 34 deletions(-) diff --git a/gcc/ChangeLog b/gcc/ChangeLog index f79f49deacb..cae34206a50 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,24 @@ +2012-04-26 David S. Miller + + * config/sparc/sparc.md (attr type): Delete 'fgm_cmp'. + (fpack16_vis, fpackfix_vis, fpack32_vis): Set type to fgm_pack. + (fmul8x16_vis, fmul8x16au_vis, fmul8x16al_vis, fmul8sux16_vis, + fmul8ulx16_vis, fmuld8sux16_vis, fmuld8ulx16_vis): Set type to + fgm_mul. + (alignaddrsi_vis, alignaddrdi_vis, alignaddrlsi_vis, + alignaddrldi_vis): Set type to gsr. + (pdist_vis, pdistn_vis): Set type to fgm_pdsit. + (fcmp_vis, cmask8_vis, + cmask16_vis, cmask32_vis, fchksm16_vis, + v3, fmean16_vis, + fp64_vis, 3, + fucmp8_vis): Set type to fga. + * config/sparc/ultra1_2.md: Remove refrences to fgm_cmp. + * config/sparc/niagara.md: Likewise. + * config/sparc/niagara2.md: Likewise. + * config/sparc/ultra3.md: Likewise, and fix type matching for + us3_ialuX reservation. + 2012-04-26 Andreas Krebbel * reload.c (find_reloads): Change the loop nesting when trying an diff --git a/gcc/config/sparc/niagara.md b/gcc/config/sparc/niagara.md index c7a2245ecfa..c7db7b9ffba 100644 --- a/gcc/config/sparc/niagara.md +++ b/gcc/config/sparc/niagara.md @@ -114,5 +114,5 @@ */ (define_insn_reservation "niag_vis" 8 (and (eq_attr "cpu" "niagara") - (eq_attr "type" "fga,fgm_pack,fgm_mul,fgm_cmp,fgm_pdist,edge,edgen,gsr,array")) + (eq_attr "type" "fga,fgm_pack,fgm_mul,fgm_pdist,edge,edgen,gsr,array")) "niag_pipe*8") diff --git a/gcc/config/sparc/niagara2.md b/gcc/config/sparc/niagara2.md index fa07becd822..59499aa0ad2 100644 --- a/gcc/config/sparc/niagara2.md +++ b/gcc/config/sparc/niagara2.md @@ -111,10 +111,10 @@ (define_insn_reservation "niag2_vis" 6 (and (eq_attr "cpu" "niagara2") - (eq_attr "type" "fga,fgm_pack,fgm_mul,fgm_cmp,fgm_pdist,edge,edgen,array,gsr")) + (eq_attr "type" "fga,fgm_pack,fgm_mul,fgm_pdist,edge,edgen,array,gsr")) "niag2_pipe*6") (define_insn_reservation "niag3_vis" 9 (and (eq_attr "cpu" "niagara3") - (eq_attr "type" "fga,fgm_pack,fgm_mul,fgm_cmp,fgm_pdist,edge,edgen,array,gsr")) + (eq_attr "type" "fga,fgm_pack,fgm_mul,fgm_pdist,edge,edgen,array,gsr")) "niag2_pipe*9") diff --git a/gcc/config/sparc/sparc.md b/gcc/config/sparc/sparc.md index c0c1ef8ac38..08cc03176d8 100644 --- a/gcc/config/sparc/sparc.md +++ b/gcc/config/sparc/sparc.md @@ -264,7 +264,7 @@ fpcmp, fpmul,fpdivs,fpdivd, fpsqrts,fpsqrtd, - fga,fgm_pack,fgm_mul,fgm_pdist,fgm_cmp,edge,edgen,gsr,array, + fga,fgm_pack,fgm_mul,fgm_pdist,edge,edgen,gsr,array, cmove, ialuX, multi,savew,flushw,iflush,trap" @@ -7925,7 +7925,7 @@ UNSPEC_FPACK16))] "TARGET_VIS" "fpack16\t%1, %0" - [(set_attr "type" "fga") + [(set_attr "type" "fgm_pack") (set_attr "fptype" "double")]) (define_insn "fpackfix_vis" @@ -7935,7 +7935,7 @@ UNSPEC_FPACKFIX))] "TARGET_VIS" "fpackfix\t%1, %0" - [(set_attr "type" "fga") + [(set_attr "type" "fgm_pack") (set_attr "fptype" "double")]) (define_insn "fpack32_vis" @@ -7946,7 +7946,7 @@ UNSPEC_FPACK32))] "TARGET_VIS" "fpack32\t%1, %2, %0" - [(set_attr "type" "fga") + [(set_attr "type" "fgm_pack") (set_attr "fptype" "double")]) (define_insn "fexpand_vis" @@ -8008,7 +8008,7 @@ UNSPEC_MUL8))] "TARGET_VIS" "fmul8x16\t%1, %2, %0" - [(set_attr "type" "fpmul") + [(set_attr "type" "fgm_mul") (set_attr "fptype" "double")]) (define_insn "fmul8x16au_vis" @@ -8018,7 +8018,7 @@ UNSPEC_MUL16AU))] "TARGET_VIS" "fmul8x16au\t%1, %2, %0" - [(set_attr "type" "fpmul") + [(set_attr "type" "fgm_mul") (set_attr "fptype" "double")]) (define_insn "fmul8x16al_vis" @@ -8028,7 +8028,7 @@ UNSPEC_MUL16AL))] "TARGET_VIS" "fmul8x16al\t%1, %2, %0" - [(set_attr "type" "fpmul") + [(set_attr "type" "fgm_mul") (set_attr "fptype" "double")]) (define_insn "fmul8sux16_vis" @@ -8038,7 +8038,7 @@ UNSPEC_MUL8SU))] "TARGET_VIS" "fmul8sux16\t%1, %2, %0" - [(set_attr "type" "fpmul") + [(set_attr "type" "fgm_mul") (set_attr "fptype" "double")]) (define_insn "fmul8ulx16_vis" @@ -8048,7 +8048,7 @@ UNSPEC_MUL8UL))] "TARGET_VIS" "fmul8ulx16\t%1, %2, %0" - [(set_attr "type" "fpmul") + [(set_attr "type" "fgm_mul") (set_attr "fptype" "double")]) (define_insn "fmuld8sux16_vis" @@ -8058,7 +8058,7 @@ UNSPEC_MULDSU))] "TARGET_VIS" "fmuld8sux16\t%1, %2, %0" - [(set_attr "type" "fpmul") + [(set_attr "type" "fgm_mul") (set_attr "fptype" "double")]) (define_insn "fmuld8ulx16_vis" @@ -8068,7 +8068,7 @@ UNSPEC_MULDUL))] "TARGET_VIS" "fmuld8ulx16\t%1, %2, %0" - [(set_attr "type" "fpmul") + [(set_attr "type" "fgm_mul") (set_attr "fptype" "double")]) (define_expand "wrgsr_vis" @@ -8149,7 +8149,8 @@ (set (zero_extract:DI (reg:DI GSR_REG) (const_int 3) (const_int 0)) (zero_extend:DI (plus:SI (match_dup 1) (match_dup 2))))] "TARGET_VIS" - "alignaddr\t%r1, %r2, %0") + "alignaddr\t%r1, %r2, %0" + [(set_attr "type" "gsr")]) (define_insn "alignaddrdi_vis" [(set (match_operand:DI 0 "register_operand" "=r") @@ -8158,7 +8159,8 @@ (set (zero_extract:DI (reg:DI GSR_REG) (const_int 3) (const_int 0)) (plus:DI (match_dup 1) (match_dup 2)))] "TARGET_VIS" - "alignaddr\t%r1, %r2, %0") + "alignaddr\t%r1, %r2, %0" + [(set_attr "type" "gsr")]) (define_insn "alignaddrlsi_vis" [(set (match_operand:SI 0 "register_operand" "=r") @@ -8168,7 +8170,8 @@ (xor:DI (zero_extend:DI (plus:SI (match_dup 1) (match_dup 2))) (const_int 7)))] "TARGET_VIS" - "alignaddrl\t%r1, %r2, %0") + "alignaddrl\t%r1, %r2, %0" + [(set_attr "type" "gsr")]) (define_insn "alignaddrldi_vis" [(set (match_operand:DI 0 "register_operand" "=r") @@ -8178,7 +8181,8 @@ (xor:DI (plus:DI (match_dup 1) (match_dup 2)) (const_int 7)))] "TARGET_VIS" - "alignaddrl\t%r1, %r2, %0") + "alignaddrl\t%r1, %r2, %0" + [(set_attr "type" "gsr")]) (define_insn "pdist_vis" [(set (match_operand:DI 0 "register_operand" "=e") @@ -8188,7 +8192,7 @@ UNSPEC_PDIST))] "TARGET_VIS" "pdist\t%1, %2, %0" - [(set_attr "type" "fga") + [(set_attr "type" "fgm_pdist") (set_attr "fptype" "double")]) ;; Edge instructions produce condition codes equivalent to a 'subcc' @@ -8270,7 +8274,7 @@ UNSPEC_FCMP))] "TARGET_VIS" "fcmp\t%1, %2, %0" - [(set_attr "type" "fpmul") + [(set_attr "type" "fga") (set_attr "fptype" "double")]) (define_expand "vcond" @@ -8460,7 +8464,8 @@ (reg:DI GSR_REG)] UNSPEC_CMASK8))] "TARGET_VIS3" - "cmask8\t%r0") + "cmask8\t%r0" + [(set_attr "type" "fga")]) (define_insn "cmask16_vis" [(set (reg:DI GSR_REG) @@ -8468,7 +8473,8 @@ (reg:DI GSR_REG)] UNSPEC_CMASK16))] "TARGET_VIS3" - "cmask16\t%r0") + "cmask16\t%r0" + [(set_attr "type" "fga")]) (define_insn "cmask32_vis" [(set (reg:DI GSR_REG) @@ -8476,7 +8482,8 @@ (reg:DI GSR_REG)] UNSPEC_CMASK32))] "TARGET_VIS3" - "cmask32\t%r0") + "cmask32\t%r0" + [(set_attr "type" "fga")]) (define_insn "fchksm16_vis" [(set (match_operand:V4HI 0 "register_operand" "=e") @@ -8484,7 +8491,8 @@ (match_operand:V4HI 2 "register_operand" "e")] UNSPEC_FCHKSM16))] "TARGET_VIS3" - "fchksm16\t%1, %2, %0") + "fchksm16\t%1, %2, %0" + [(set_attr "type" "fga")]) (define_code_iterator vis3_shift [ashift ss_ashift lshiftrt ashiftrt]) (define_code_attr vis3_shift_insn @@ -8497,7 +8505,8 @@ (vis3_shift:GCM (match_operand:GCM 1 "register_operand" "") (match_operand:GCM 2 "register_operand" "")))] "TARGET_VIS3" - "\t%1, %2, %0") + "\t%1, %2, %0" + [(set_attr "type" "fga")]) (define_insn "pdistn_vis" [(set (match_operand:P 0 "register_operand" "=r") @@ -8505,7 +8514,9 @@ (match_operand:V8QI 2 "register_operand" "e")] UNSPEC_PDISTN))] "TARGET_VIS3" - "pdistn\t%1, %2, %0") + "pdistn\t%1, %2, %0" + [(set_attr "type" "fgm_pdist") + (set_attr "fptype" "double")]) (define_insn "fmean16_vis" [(set (match_operand:V4HI 0 "register_operand" "=e") @@ -8521,14 +8532,16 @@ (const_int 1) (const_int 1)])) (const_int 1))))] "TARGET_VIS3" - "fmean16\t%1, %2, %0") + "fmean16\t%1, %2, %0" + [(set_attr "type" "fga")]) (define_insn "fp64_vis" [(set (match_operand:V1DI 0 "register_operand" "=e") (plusminus:V1DI (match_operand:V1DI 1 "register_operand" "e") (match_operand:V1DI 2 "register_operand" "e")))] "TARGET_VIS3" - "fp64\t%1, %2, %0") + "fp64\t%1, %2, %0" + [(set_attr "type" "fga")]) (define_mode_iterator VASS [V4HI V2SI V2HI V1SI]) (define_code_iterator vis3_addsub_ss [ss_plus ss_minus]) @@ -8542,7 +8555,8 @@ (vis3_addsub_ss:VASS (match_operand:VASS 1 "register_operand" "") (match_operand:VASS 2 "register_operand" "")))] "TARGET_VIS3" - "\t%1, %2, %0") + "\t%1, %2, %0" + [(set_attr "type" "fga")]) (define_insn "fucmp8_vis" [(set (match_operand:P 0 "register_operand" "=r") @@ -8550,7 +8564,8 @@ (match_operand:V8QI 2 "register_operand" "e"))] UNSPEC_FUCMP))] "TARGET_VIS3" - "fucmp8\t%1, %2, %0") + "fucmp8\t%1, %2, %0" + [(set_attr "type" "fga")]) (define_insn "*naddsf3" [(set (match_operand:SF 0 "register_operand" "=f") diff --git a/gcc/config/sparc/ultra1_2.md b/gcc/config/sparc/ultra1_2.md index 9cdebab620b..be26ea8d32f 100644 --- a/gcc/config/sparc/ultra1_2.md +++ b/gcc/config/sparc/ultra1_2.md @@ -275,7 +275,7 @@ 4 (and (and (eq_attr "cpu" "ultrasparc") - (eq_attr "type" "fgm_pack,fgm_mul,fgm_cmp")) + (eq_attr "type" "fgm_pack,fgm_mul")) (eq_attr "fptype" "single")) "us1_fpm + us1_fp_single + us1_slotany, nothing*3") @@ -285,7 +285,7 @@ 4 (and (and (eq_attr "cpu" "ultrasparc") - (eq_attr "type" "fgm_pack,fgm_mul,fgm_cmp")) + (eq_attr "type" "fgm_pack,fgm_mul")) (eq_attr "fptype" "double")) "us1_fpm + us1_fp_double + us1_slotany, nothing*3") diff --git a/gcc/config/sparc/ultra3.md b/gcc/config/sparc/ultra3.md index c891e356205..fc36e252b69 100644 --- a/gcc/config/sparc/ultra3.md +++ b/gcc/config/sparc/ultra3.md @@ -46,7 +46,7 @@ (define_insn_reservation "us3_ialuX" 5 (and (eq_attr "cpu" "ultrasparc3") - (eq_attr "type" "ialu,shift,compare")) + (eq_attr "type" "ialuX")) "us3_single_issue*4, nothing") (define_insn_reservation "us3_cmove" 2 @@ -182,7 +182,7 @@ (define_insn_reservation "us3_fgm" 4 (and (eq_attr "cpu" "ultrasparc3") - (eq_attr "type" "fgm_pack,fgm_mul,fgm_cmp")) + (eq_attr "type" "fgm_pack,fgm_mul")) "us3_fpm + us3_slotany, nothing*3") (define_insn_reservation "us3_pdist" -- 2.30.2