From afa9b889aee9028ac72efeb59214728cbacdc230 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Sun, 12 Apr 2015 22:09:46 +0200 Subject: [PATCH] liteeth/phy/gmii: fix clock generation for mii mode (clock_pads.tx is an input) --- misoclib/com/liteeth/phy/gmii.py | 20 ++++++++++++++------ misoclib/com/liteeth/phy/gmii_mii.py | 2 +- 2 files changed, 15 insertions(+), 7 deletions(-) diff --git a/misoclib/com/liteeth/phy/gmii.py b/misoclib/com/liteeth/phy/gmii.py index 429eea62..242da110 100644 --- a/misoclib/com/liteeth/phy/gmii.py +++ b/misoclib/com/liteeth/phy/gmii.py @@ -40,16 +40,24 @@ class LiteEthPHYGMIIRX(Module): self.comb += source.eop.eq(eop) class LiteEthPHYGMIICRG(Module, AutoCSR): - def __init__(self, clock_pads, pads, with_hw_init_reset): + def __init__(self, clock_pads, pads, with_hw_init_reset, mii_mode=0): self._reset = CSRStorage() ### self.clock_domains.cd_eth_rx = ClockDomain() self.clock_domains.cd_eth_tx = ClockDomain() - self.specials += DDROutput(1, 0, clock_pads.gtx, ClockSignal("eth_tx")) - self.comb += [ - self.cd_eth_rx.clk.eq(clock_pads.rx), # Let the synthesis tool insert - self.cd_eth_tx.clk.eq(self.cd_eth_rx.clk) # the appropriate clock buffer - ] + + # RX : Let the synthesis tool insert the appropriate clock buffer + self.comb += self.cd_eth_rx.clk.eq(clock_pads.rx) + + # TX : GMII: Drive clock_pads.gtx, clock_pads.tx unused + # MII: Use PHY clock_pads.tx as eth_tx_clk, do not drive clock_pads.gtx + self.specials += DDROutput(1, mii_mode, clock_pads.gtx, ClockSignal("eth_tx")) + # XXX Xilinx specific, replace BUFGMUX with a generic clock buffer? + self.specials += Instance("BUFGMUX", + i_I0=self.cd_eth_rx.clk, + i_I1=clock_pads.tx, + i_S=mii_mode, + o_O=self.cd_eth_tx.clk) if with_hw_init_reset: reset = Signal() diff --git a/misoclib/com/liteeth/phy/gmii_mii.py b/misoclib/com/liteeth/phy/gmii_mii.py index 5f1229e1..32a3ae91 100644 --- a/misoclib/com/liteeth/phy/gmii_mii.py +++ b/misoclib/com/liteeth/phy/gmii_mii.py @@ -94,7 +94,7 @@ class LiteEthPHYGMIIMII(Module, AutoCSR): self._mode = CSRStorage() mode = self._mode.storage # Note: we can use GMII CRG since it also handles tx clock pad used for MII - self.submodules.crg = LiteEthPHYGMIICRG(clock_pads, pads, with_hw_init_reset) + self.submodules.crg = LiteEthPHYGMIICRG(clock_pads, pads, with_hw_init_reset, mode==modes["MII"]) self.submodules.clock_counter = LiteEthGMIIMIIClockCounter() self.submodules.tx = RenameClockDomains(LiteEthPHYGMIIMIITX(pads, mode), "eth_tx") self.submodules.rx = RenameClockDomains(LiteEthPHYGMIIMIIRX(pads, mode), "eth_rx") -- 2.30.2