From afc69d4efe3e4b2ca974fa4c54942e0f40266fcf Mon Sep 17 00:00:00 2001 From: Segher Boessenkool Date: Mon, 20 May 2019 02:09:34 +0200 Subject: [PATCH] rs6000: Delete the "wo" constraint This replaces the "wo" constraint by "wa", with isa "p9v". * config/rs6000/constraints.md (define_register_constraint "wo"): Delete. * config/rs6000/rs6000.h (enum r6000_reg_class_enum): Delete RS6000_CONSTRAINT_wo. * config/rs6000/rs6000.c (rs6000_debug_reg_global): Adjust. (rs6000_init_hard_regno_mode_ok): Adjust. * config/rs6000/rs6000.md: Replace "wo" constraint by "wa" with "p9v". * config/rs6000/altivec.md: Ditto. * doc/md.texi (Machine Constraints): Adjust. From-SVN: r271385 --- gcc/ChangeLog | 12 +++++++ gcc/config/rs6000/altivec.md | 54 ++++++++++++++++++-------------- gcc/config/rs6000/constraints.md | 3 -- gcc/config/rs6000/rs6000.c | 11 ++----- gcc/config/rs6000/rs6000.h | 1 - gcc/config/rs6000/rs6000.md | 40 +++++++++++++++-------- gcc/config/rs6000/vsx.md | 23 +++++++++----- gcc/doc/md.texi | 5 +-- 8 files changed, 87 insertions(+), 62 deletions(-) diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 727fa43d2b4..170f8fc2ae4 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,15 @@ +2019-05-19 Segher Boessenkool + + * config/rs6000/constraints.md (define_register_constraint "wo"): + Delete. + * config/rs6000/rs6000.h (enum r6000_reg_class_enum): Delete + RS6000_CONSTRAINT_wo. + * config/rs6000/rs6000.c (rs6000_debug_reg_global): Adjust. + (rs6000_init_hard_regno_mode_ok): Adjust. + * config/rs6000/rs6000.md: Replace "wo" constraint by "wa" with "p9v". + * config/rs6000/altivec.md: Ditto. + * doc/md.texi (Machine Constraints): Adjust. + 2019-05-18 Iain Sandoe * config/darwin-c.c (darwin_register_objc_includes): Do not diff --git a/gcc/config/rs6000/altivec.md b/gcc/config/rs6000/altivec.md index 4a1150e0994..b6a22d9010c 100644 --- a/gcc/config/rs6000/altivec.md +++ b/gcc/config/rs6000/altivec.md @@ -2023,28 +2023,30 @@ ;; Slightly prefer vperm, since the target does not overlap the source (define_insn "altivec_vperm__direct" - [(set (match_operand:VM 0 "register_operand" "=v,?wo") - (unspec:VM [(match_operand:VM 1 "register_operand" "v,wo") + [(set (match_operand:VM 0 "register_operand" "=v,?wa") + (unspec:VM [(match_operand:VM 1 "register_operand" "v,wa") (match_operand:VM 2 "register_operand" "v,0") - (match_operand:V16QI 3 "register_operand" "v,wo")] + (match_operand:V16QI 3 "register_operand" "v,wa")] UNSPEC_VPERM))] "TARGET_ALTIVEC" "@ vperm %0,%1,%2,%3 xxperm %x0,%x1,%x3" - [(set_attr "type" "vecperm")]) + [(set_attr "type" "vecperm") + (set_attr "isa" "*,p9v")]) (define_insn "altivec_vperm_v8hiv16qi" - [(set (match_operand:V16QI 0 "register_operand" "=v,?wo") - (unspec:V16QI [(match_operand:V8HI 1 "register_operand" "v,wo") + [(set (match_operand:V16QI 0 "register_operand" "=v,?wa") + (unspec:V16QI [(match_operand:V8HI 1 "register_operand" "v,wa") (match_operand:V8HI 2 "register_operand" "v,0") - (match_operand:V16QI 3 "register_operand" "v,wo")] + (match_operand:V16QI 3 "register_operand" "v,wa")] UNSPEC_VPERM))] "TARGET_ALTIVEC" "@ vperm %0,%1,%2,%3 xxperm %x0,%x1,%x3" - [(set_attr "type" "vecperm")]) + [(set_attr "type" "vecperm") + (set_attr "isa" "*,p9v")]) (define_expand "altivec_vperm__uns" [(set (match_operand:VM 0 "register_operand") @@ -2062,16 +2064,17 @@ }) (define_insn "*altivec_vperm__uns_internal" - [(set (match_operand:VM 0 "register_operand" "=v,?wo") - (unspec:VM [(match_operand:VM 1 "register_operand" "v,wo") + [(set (match_operand:VM 0 "register_operand" "=v,?wa") + (unspec:VM [(match_operand:VM 1 "register_operand" "v,wa") (match_operand:VM 2 "register_operand" "v,0") - (match_operand:V16QI 3 "register_operand" "v,wo")] + (match_operand:V16QI 3 "register_operand" "v,wa")] UNSPEC_VPERM_UNS))] "TARGET_ALTIVEC" "@ vperm %0,%1,%2,%3 xxperm %x0,%x1,%x3" - [(set_attr "type" "vecperm")]) + [(set_attr "type" "vecperm") + (set_attr "isa" "*,p9v")]) (define_expand "vec_permv16qi" [(set (match_operand:V16QI 0 "register_operand") @@ -2088,16 +2091,17 @@ }) (define_insn "*altivec_vpermr__internal" - [(set (match_operand:VM 0 "register_operand" "=v,?wo") - (unspec:VM [(match_operand:VM 1 "register_operand" "v,wo") + [(set (match_operand:VM 0 "register_operand" "=v,?wa") + (unspec:VM [(match_operand:VM 1 "register_operand" "v,wa") (match_operand:VM 2 "register_operand" "v,0") - (match_operand:V16QI 3 "register_operand" "v,wo")] + (match_operand:V16QI 3 "register_operand" "v,wa")] UNSPEC_VPERMR))] "TARGET_P9_VECTOR" "@ vpermr %0,%1,%2,%3 xxpermr %x0,%x1,%x3" - [(set_attr "type" "vecperm")]) + [(set_attr "type" "vecperm") + (set_attr "isa" "*,p9v")]) (define_insn "altivec_vrfip" ; ceil [(set (match_operand:V4SF 0 "register_operand" "=v") @@ -3245,28 +3249,30 @@ "") (define_insn "vperm_v8hiv4si" - [(set (match_operand:V4SI 0 "register_operand" "=v,?wo") - (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v,wo") + [(set (match_operand:V4SI 0 "register_operand" "=v,?wa") + (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v,wa") (match_operand:V4SI 2 "register_operand" "v,0") - (match_operand:V16QI 3 "register_operand" "v,wo")] + (match_operand:V16QI 3 "register_operand" "v,wa")] UNSPEC_VPERMSI))] "TARGET_ALTIVEC" "@ vperm %0,%1,%2,%3 xxperm %x0,%x1,%x3" - [(set_attr "type" "vecperm")]) + [(set_attr "type" "vecperm") + (set_attr "isa" "*,p9v")]) (define_insn "vperm_v16qiv8hi" - [(set (match_operand:V8HI 0 "register_operand" "=v,?wo") - (unspec:V8HI [(match_operand:V16QI 1 "register_operand" "v,wo") + [(set (match_operand:V8HI 0 "register_operand" "=v,?wa") + (unspec:V8HI [(match_operand:V16QI 1 "register_operand" "v,wa") (match_operand:V8HI 2 "register_operand" "v,0") - (match_operand:V16QI 3 "register_operand" "v,wo")] + (match_operand:V16QI 3 "register_operand" "v,wa")] UNSPEC_VPERMHI))] "TARGET_ALTIVEC" "@ vperm %0,%1,%2,%3 xxperm %x0,%x1,%x3" - [(set_attr "type" "vecperm")]) + [(set_attr "type" "vecperm") + (set_attr "isa" "*,p9v")]) (define_expand "vec_unpacku_hi_v16qi" diff --git a/gcc/config/rs6000/constraints.md b/gcc/config/rs6000/constraints.md index 27db92bf0d6..c11dc0eb65c 100644 --- a/gcc/config/rs6000/constraints.md +++ b/gcc/config/rs6000/constraints.md @@ -97,9 +97,6 @@ ;; There is a mode_attr that resolves to wm for SDmode and wn for SFmode (define_register_constraint "wn" "NO_REGS" "No register (NO_REGS).") -(define_register_constraint "wo" "rs6000_constraints[RS6000_CONSTRAINT_wo]" - "VSX register if the -mpower9-vector option was used or NO_REGS.") - (define_register_constraint "wp" "rs6000_constraints[RS6000_CONSTRAINT_wp]" "VSX register to use for IEEE 128-bit fp TFmode, or NO_REGS.") diff --git a/gcc/config/rs6000/rs6000.c b/gcc/config/rs6000/rs6000.c index 6cbff912606..18fa3acb2e1 100644 --- a/gcc/config/rs6000/rs6000.c +++ b/gcc/config/rs6000/rs6000.c @@ -2519,7 +2519,6 @@ rs6000_debug_reg_global (void) "wk reg_class = %s\n" "wl reg_class = %s\n" "wm reg_class = %s\n" - "wo reg_class = %s\n" "wp reg_class = %s\n" "wq reg_class = %s\n" "wr reg_class = %s\n" @@ -2552,7 +2551,6 @@ rs6000_debug_reg_global (void) reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wk]], reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wl]], reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wm]], - reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wo]], reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wp]], reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wq]], reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wr]], @@ -3266,14 +3264,9 @@ rs6000_init_hard_regno_mode_ok (bool global_init_p) rs6000_constraints[RS6000_CONSTRAINT_wp] = VSX_REGS; /* TFmode */ } + /* Support for new D-form instructions. */ if (TARGET_P9_VECTOR) - { - /* Support for new D-form instructions. */ - rs6000_constraints[RS6000_CONSTRAINT_wb] = ALTIVEC_REGS; - - /* Support for ISA 3.0 (power9) vectors. */ - rs6000_constraints[RS6000_CONSTRAINT_wo] = VSX_REGS; - } + rs6000_constraints[RS6000_CONSTRAINT_wb] = ALTIVEC_REGS; /* Support for new direct moves (ISA 3.0 + 64bit). */ if (TARGET_DIRECT_MOVE_128) diff --git a/gcc/config/rs6000/rs6000.h b/gcc/config/rs6000/rs6000.h index 68ef491ac0c..d59f4c702d3 100644 --- a/gcc/config/rs6000/rs6000.h +++ b/gcc/config/rs6000/rs6000.h @@ -1260,7 +1260,6 @@ enum r6000_reg_class_enum { RS6000_CONSTRAINT_wk, /* FPR/VSX register for DFmode direct moves. */ RS6000_CONSTRAINT_wl, /* FPR register for LFIWAX */ RS6000_CONSTRAINT_wm, /* VSX register for direct move */ - RS6000_CONSTRAINT_wo, /* VSX register for power9 vector. */ RS6000_CONSTRAINT_wp, /* VSX reg for IEEE 128-bit fp TFmode. */ RS6000_CONSTRAINT_wq, /* VSX reg for IEEE 128-bit fp KFmode. */ RS6000_CONSTRAINT_wr, /* GPR register if 64-bit */ diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md index 0906ccb0167..c56c58585fd 100644 --- a/gcc/config/rs6000/rs6000.md +++ b/gcc/config/rs6000/rs6000.md @@ -2463,9 +2463,9 @@ [(set_attr "type" "store")]) (define_insn_and_split "bswaphi2_reg" - [(set (match_operand:HI 0 "gpc_reg_operand" "=&r,wo") + [(set (match_operand:HI 0 "gpc_reg_operand" "=&r,wa") (bswap:HI - (match_operand:HI 1 "gpc_reg_operand" "r,wo"))) + (match_operand:HI 1 "gpc_reg_operand" "r,wa"))) (clobber (match_scratch:SI 2 "=&r,X"))] "" "@ @@ -2488,14 +2488,15 @@ operands[4] = simplify_gen_subreg (SImode, operands[1], HImode, 0); } [(set_attr "length" "12,4") - (set_attr "type" "*,vecperm")]) + (set_attr "type" "*,vecperm") + (set_attr "isa" "*,p9v")]) ;; We are always BITS_BIG_ENDIAN, so the bit positions below in ;; zero_extract insns do not change for -mlittle. (define_insn_and_split "bswapsi2_reg" - [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,wo") + [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,wa") (bswap:SI - (match_operand:SI 1 "gpc_reg_operand" "r,wo")))] + (match_operand:SI 1 "gpc_reg_operand" "r,wa")))] "" "@ # @@ -2518,7 +2519,8 @@ (const_int -256))))] "" [(set_attr "length" "12,4") - (set_attr "type" "*,vecperm")]) + (set_attr "type" "*,vecperm") + (set_attr "isa" "*,p9v")]) ;; On systems with LDBRX/STDBRX generate the loads/stores directly, just like ;; we do for L{H,W}BRX and ST{H,W}BRX above. If not, we have to generate more @@ -2583,11 +2585,12 @@ [(set_attr "type" "store")]) (define_insn "bswapdi2_xxbrd" - [(set (match_operand:DI 0 "gpc_reg_operand" "=wo") - (bswap:DI (match_operand:DI 1 "gpc_reg_operand" "wo")))] + [(set (match_operand:DI 0 "gpc_reg_operand" "=wa") + (bswap:DI (match_operand:DI 1 "gpc_reg_operand" "wa")))] "TARGET_P9_VECTOR" "xxbrd %x0,%x1" - [(set_attr "type" "vecperm")]) + [(set_attr "type" "vecperm") + (set_attr "isa" "p9v")]) (define_insn "bswapdi2_reg" [(set (match_operand:DI 0 "gpc_reg_operand" "=&r") @@ -8706,7 +8709,7 @@ [(set (match_operand:DI 0 "nonimmediate_operand" "=Y, r, r, m, ^d, ^d, r, wY, Z, ^wb, $wv, ^wi, - wo, wo, wv, wi, *i, wv, + wa, wa, wv, wi, *i, wv, wv") (match_operand:DI 1 "input_operand" @@ -8748,7 +8751,12 @@ "8, 8, 8, 4, 4, 4, 16, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 8, - 4")]) + 4") + (set_attr "isa" + "*, *, *, *, *, *, + *, *, *, *, *, *, + p9v, p9v, *, *, *, *, + *")]) (define_split [(set (match_operand:DI 0 "gpc_reg_operand") @@ -8786,7 +8794,7 @@ [(set (match_operand:DI 0 "nonimmediate_operand" "=YZ, r, r, r, r, r, m, ^d, ^d, wY, Z, $wb, - $wv, ^wi, wo, wo, wv, wi, + $wv, ^wi, wa, wa, wv, wi, wi, wv, wv, r, *h, *h, ?r, ?wg, ?r, ?wj") @@ -8842,7 +8850,13 @@ 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 8, 4, 4, 4, 4, - 4, 4, 4, 4")]) + 4, 4, 4, 4") + (set_attr "isa" + "*, *, *, *, *, *, + *, *, *, *, *, *, + *, *, p9v, p9v, *, *, + *, *, *, *, *, *, + *, *, *, *")]) ; Some DImode loads are best done as a load of -1 followed by a mask ; instruction. diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md index 80434d10247..df8951e3555 100644 --- a/gcc/config/rs6000/vsx.md +++ b/gcc/config/rs6000/vsx.md @@ -1209,7 +1209,7 @@ (define_insn "vsx_mov_64bit" [(set (match_operand:VSX_M 0 "nonimmediate_operand" "=ZwO, , , r, we, ?wQ, - ?&r, ??r, ??Y, , wo, v, + ?&r, ??r, ??Y, , wa, v, ?, v, , wZ, v") (match_operand:VSX_M 1 "input_operand" @@ -1227,11 +1227,14 @@ "vecstore, vecload, vecsimple, mffgpr, mftgpr, load, store, load, store, *, vecsimple, vecsimple, vecsimple, *, *, vecstore, vecload") - (set_attr "length" "4, 4, 4, 8, 4, 8, 8, 8, 8, 8, 4, 4, - 4, 20, 8, 4, 4")]) + 4, 20, 8, 4, 4") + (set_attr "isa" + "*, *, *, *, *, *, + *, *, *, *, p9v, *, + *, *, *, *, *")]) ;; VSX store VSX load VSX move GPR load GPR store GPR move ;; XXSPLTIB VSPLTISW VSX 0/-1 VMX const GPR const @@ -1239,7 +1242,7 @@ (define_insn "*vsx_mov_32bit" [(set (match_operand:VSX_M 0 "nonimmediate_operand" "=ZwO, , , ??r, ??Y, , - wo, v, ?, v, , + wa, v, ?, v, , wZ, v") (match_operand:VSX_M 1 "input_operand" @@ -1257,11 +1260,14 @@ "vecstore, vecload, vecsimple, load, store, *, vecsimple, vecsimple, vecsimple, *, *, vecstore, vecload") - (set_attr "length" "4, 4, 4, 16, 16, 16, 4, 4, 4, 20, 16, - 4, 4")]) + 4, 4") + (set_attr "isa" + "*, *, *, *, *, *, + p9v, *, *, *, *, + *, *")]) ;; Explicit load/store expanders for the builtin functions (define_expand "vsx_load_" @@ -3199,7 +3205,7 @@ [(set (match_operand: 0 "gpc_reg_operand" "=d, d, wr, wr") (vec_select: - (match_operand:VSX_D 1 "gpc_reg_operand" ", , wm, wo") + (match_operand:VSX_D 1 "gpc_reg_operand" ", , wm, wa") (parallel [(match_operand:QI 2 "const_0_to_1_operand" "wD, n, wD, n")])))] @@ -3248,7 +3254,8 @@ else gcc_unreachable (); } - [(set_attr "type" "veclogical,mftgpr,mftgpr,vecperm")]) + [(set_attr "type" "veclogical,mftgpr,mftgpr,vecperm") + (set_attr "isa" "*,*,*,p9v")]) ;; Optimize extracting a single scalar element from memory. (define_insn_and_split "*vsx_extract___load" diff --git a/gcc/doc/md.texi b/gcc/doc/md.texi index b35bcaace00..dc58aa9d2b6 100644 --- a/gcc/doc/md.texi +++ b/gcc/doc/md.texi @@ -3198,7 +3198,7 @@ Any VSX register if the @option{-mvsx} option was used or NO_REGS. When using any of the register constraints (@code{wa}, @code{wd}, @code{wf}, @code{wg}, @code{wh}, @code{wi}, @code{wj}, @code{wk}, -@code{wl}, @code{wm}, @code{wo}, @code{wp}, @code{wq}, @code{ws}, +@code{wl}, @code{wm}, @code{wp}, @code{wq}, @code{ws}, @code{wt}, @code{wu}, @code{wv}, @code{ww}, or @code{wy}) that take VSX registers, you must use @code{%x} in the template so that the correct register is used. Otherwise the register number @@ -3283,9 +3283,6 @@ VSX register if direct move instructions are enabled, or NO_REGS. @item wn No register (NO_REGS). -@item wo -VSX register to use for ISA 3.0 vector instructions, or NO_REGS. - @item wp VSX register to use for IEEE 128-bit floating point TFmode, or NO_REGS. -- 2.30.2