From afe006ad4deda8faeb9648913310c819aa250760 Mon Sep 17 00:00:00 2001 From: Terry Guo Date: Thu, 26 Feb 2015 04:03:22 +0000 Subject: [PATCH] arm-cores.def (cortex-m7): Add flag FL_NO_VOLATILE_CE. gcc/ * config/arm/arm-cores.def (cortex-m7): Add flag FL_NO_VOLATILE_CE. * config/arm/arm-protos.h (FL_NO_VOLATILE_CE): New flag. (arm_arch_no_volatile_ce): Declare new global variable. * config/arm/arm.c (arm_arch_no_volatile_ce): New global variable. (arm_option_override): Assign value to arm_arch_no_volatile_ce. * config/arm/arm.h (arm_arch_no_volatile_ce): Declare it. (TARGET_NO_VOLATILE_CE): New macro. * config/arm/arm.md (arm_comparison_operator): Disabled if not allow volatile memory access in IT block gcc/testsuite/ * gcc.target/arm/no-volatile-in-it.c: New test. From-SVN: r220999 --- gcc/ChangeLog | 12 ++++++++++++ gcc/config/arm/arm-cores.def | 2 +- gcc/config/arm/arm-protos.h | 4 ++++ gcc/config/arm/arm.c | 4 ++++ gcc/config/arm/arm.h | 6 ++++++ gcc/config/arm/arm.md | 3 ++- gcc/testsuite/ChangeLog | 4 ++++ gcc/testsuite/gcc.target/arm/no-volatile-in-it.c | 14 ++++++++++++++ 8 files changed, 47 insertions(+), 2 deletions(-) create mode 100644 gcc/testsuite/gcc.target/arm/no-volatile-in-it.c diff --git a/gcc/ChangeLog b/gcc/ChangeLog index cb196f7c159..1ff9ac6f2c5 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,15 @@ +2015-02-26 Terry Guo + + * config/arm/arm-cores.def (cortex-m7): Add flag FL_NO_VOLATILE_CE. + * config/arm/arm-protos.h (FL_NO_VOLATILE_CE): New flag. + (arm_arch_no_volatile_ce): Declare new global variable. + * config/arm/arm.c (arm_arch_no_volatile_ce): New global variable. + (arm_option_override): Assign value to arm_arch_no_volatile_ce. + * config/arm/arm.h (arm_arch_no_volatile_ce): Declare it. + (TARGET_NO_VOLATILE_CE): New macro. + * config/arm/arm.md (arm_comparison_operator): Disabled if not allow + volatile memory access in IT block + 2015-02-25 Uros Bizjak PR target/47230 diff --git a/gcc/config/arm/arm-cores.def b/gcc/config/arm/arm-cores.def index d7e730d77f3..b22ea7fd6d4 100644 --- a/gcc/config/arm/arm-cores.def +++ b/gcc/config/arm/arm-cores.def @@ -155,7 +155,7 @@ ARM_CORE("cortex-r4", cortexr4, cortexr4, 7R, FL_LDSCHED, cortex) ARM_CORE("cortex-r4f", cortexr4f, cortexr4f, 7R, FL_LDSCHED, cortex) ARM_CORE("cortex-r5", cortexr5, cortexr5, 7R, FL_LDSCHED | FL_ARM_DIV, cortex) ARM_CORE("cortex-r7", cortexr7, cortexr7, 7R, FL_LDSCHED | FL_ARM_DIV, cortex) -ARM_CORE("cortex-m7", cortexm7, cortexm7, 7EM, FL_LDSCHED, cortex_m7) +ARM_CORE("cortex-m7", cortexm7, cortexm7, 7EM, FL_LDSCHED | FL_NO_VOLATILE_CE, cortex_m7) ARM_CORE("cortex-m4", cortexm4, cortexm4, 7EM, FL_LDSCHED, v7m) ARM_CORE("cortex-m3", cortexm3, cortexm3, 7M, FL_LDSCHED, v7m) ARM_CORE("marvell-pj4", marvell_pj4, marvell_pj4, 7A, FL_LDSCHED, 9e) diff --git a/gcc/config/arm/arm-protos.h b/gcc/config/arm/arm-protos.h index 307babb70f0..28ffe52e8e7 100644 --- a/gcc/config/arm/arm-protos.h +++ b/gcc/config/arm/arm-protos.h @@ -360,6 +360,7 @@ extern bool arm_is_constant_pool_ref (rtx); #define FL_CRC32 (1 << 25) /* ARMv8 CRC32 instructions. */ #define FL_SMALLMUL (1 << 26) /* Small multiply supported. */ +#define FL_NO_VOLATILE_CE (1 << 27) /* No volatile memory in IT block. */ #define FL_IWMMXT (1 << 29) /* XScale v2 or "Intel Wireless MMX technology". */ #define FL_IWMMXT2 (1 << 30) /* "Intel Wireless MMX2 technology". */ @@ -482,6 +483,9 @@ extern int arm_arch_thumb2; extern int arm_arch_arm_hwdiv; extern int arm_arch_thumb_hwdiv; +/* Nonzero if chip disallows volatile memory access in IT block. */ +extern int arm_arch_no_volatile_ce; + /* Nonzero if we should use Neon to handle 64-bits operations rather than core registers. */ extern int prefer_neon_for_64bits; diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c index 7bf5b4dfcc7..f7063bc06fa 100644 --- a/gcc/config/arm/arm.c +++ b/gcc/config/arm/arm.c @@ -866,6 +866,9 @@ int arm_arch_thumb2; int arm_arch_arm_hwdiv; int arm_arch_thumb_hwdiv; +/* Nonzero if chip disallows volatile memory access in IT block. */ +int arm_arch_no_volatile_ce; + /* Nonzero if we should use Neon to handle 64-bits operations rather than core registers. */ int prefer_neon_for_64bits = 0; @@ -2859,6 +2862,7 @@ arm_option_override (void) arm_arch_iwmmxt2 = (insn_flags & FL_IWMMXT2) != 0; arm_arch_thumb_hwdiv = (insn_flags & FL_THUMB_DIV) != 0; arm_arch_arm_hwdiv = (insn_flags & FL_ARM_DIV) != 0; + arm_arch_no_volatile_ce = (insn_flags & FL_NO_VOLATILE_CE) != 0; arm_tune_cortex_a9 = (arm_tune == cortexa9) != 0; arm_arch_crc = (insn_flags & FL_CRC32) != 0; arm_m_profile_small_mul = (insn_flags & FL_SMALLMUL) != 0; diff --git a/gcc/config/arm/arm.h b/gcc/config/arm/arm.h index 297dfe1ae67..8c10ea3c905 100644 --- a/gcc/config/arm/arm.h +++ b/gcc/config/arm/arm.h @@ -383,6 +383,9 @@ extern void (*arm_lang_output_object_attributes_hook)(void); #define TARGET_IDIV ((TARGET_ARM && arm_arch_arm_hwdiv) \ || (TARGET_THUMB2 && arm_arch_thumb_hwdiv)) +/* Nonzero if disallow volatile memory access in IT block. */ +#define TARGET_NO_VOLATILE_CE (arm_arch_no_volatile_ce) + /* Should NEON be used for 64-bits bitops. */ #define TARGET_PREFER_NEON_64BITS (prefer_neon_for_64bits) @@ -568,6 +571,9 @@ extern int arm_arch_arm_hwdiv; /* Nonzero if chip supports integer division instruction in Thumb mode. */ extern int arm_arch_thumb_hwdiv; +/* Nonzero if chip disallows volatile memory access in IT block. */ +extern int arm_arch_no_volatile_ce; + /* Nonzero if we should use Neon to handle 64-bits operations rather than core registers. */ extern int prefer_neon_for_64bits; diff --git a/gcc/config/arm/arm.md b/gcc/config/arm/arm.md index c13e9b223e3..164ac13a262 100644 --- a/gcc/config/arm/arm.md +++ b/gcc/config/arm/arm.md @@ -10755,7 +10755,8 @@ [(match_operator 0 "arm_comparison_operator" [(match_operand 1 "cc_register" "") (const_int 0)])] - "TARGET_32BIT" + "TARGET_32BIT + && (!TARGET_NO_VOLATILE_CE || !volatile_refs_p (PATTERN (insn)))" "" [(set_attr "predicated" "yes")] ) diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index a0f39711027..faece1f1dac 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,7 @@ +2015-02-26 Terry Guo + + * gcc.target/arm/no-volatile-in-it.c: New test. + 2015-02-25 Peter Bergner * gcc.target/powerpc/htm-builtin-1.c (dg-do) Change to assemble. diff --git a/gcc/testsuite/gcc.target/arm/no-volatile-in-it.c b/gcc/testsuite/gcc.target/arm/no-volatile-in-it.c new file mode 100644 index 00000000000..206afdbd0fd --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/no-volatile-in-it.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_thumb2_ok } */ +/* { dg-options "-Os -mthumb -mcpu=cortex-m7" } */ + +int +foo (int a, int b, volatile int *c, volatile int *d) +{ + if (a > b) + return c[0]; + else + return d[0]; +} + +/* { dg-final { scan-assembler-not "ldrgt" } } */ -- 2.30.2