From afe1f36b42929a7150bacb3dfb4c1fe61866eed9 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Sat, 18 Dec 2021 01:19:40 +0000 Subject: [PATCH] tlb_req_index is TLB_BITS long not TLB_SIZE --- src/soc/experiment/icache.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/soc/experiment/icache.py b/src/soc/experiment/icache.py index f66e2210..3a80e430 100644 --- a/src/soc/experiment/icache.py +++ b/src/soc/experiment/icache.py @@ -824,7 +824,7 @@ class ICache(FetchUnitInterface, Elaboratable): req_is_miss = Signal() req_laddr = Signal(64) - tlb_req_index = Signal(TLB_SIZE) + tlb_req_index = Signal(TLB_BITS) real_addr = Signal(REAL_ADDR_BITS) ra_valid = Signal() priv_fault = Signal() -- 2.30.2