From afe9d6d08cf88ebeb0395d465176e88408c97a48 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Wed, 27 Mar 2019 13:20:20 +0000 Subject: [PATCH] whitespace cleanup --- src/add/test_prioritymux_pipe.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/add/test_prioritymux_pipe.py b/src/add/test_prioritymux_pipe.py index 6b41f1b4..d2167366 100644 --- a/src/add/test_prioritymux_pipe.py +++ b/src/add/test_prioritymux_pipe.py @@ -7,7 +7,6 @@ from nmigen.cli import verilog, rtlil from multipipe import CombMultiInPipeline, InputPriorityArbiter - class PriorityUnbufferedPipeline(CombMultiInPipeline): def __init__(self, stage, p_len=4): p_mux = InputPriorityArbiter(self, p_len) @@ -17,6 +16,7 @@ class PriorityUnbufferedPipeline(CombMultiInPipeline): return self.p_mux.ports() #return UnbufferedPipeline.ports(self) + self.p_mux.ports() + class PassData: def __init__(self): self.mid = Signal(2, reset_less=True) -- 2.30.2