From b0144b300face91825af1e1e38f3015579c93b0a Mon Sep 17 00:00:00 2001 From: Cesar Strauss Date: Sun, 21 Feb 2021 06:58:54 -0300 Subject: [PATCH] Use symbolic values as field sizes --- src/soc/decoder/isa/caller.py | 11 +++++++++++ src/soc/sv/trans/svp64.py | 29 ++++++++++++++++++----------- 2 files changed, 29 insertions(+), 11 deletions(-) diff --git a/src/soc/decoder/isa/caller.py b/src/soc/decoder/isa/caller.py index c78219d8..08deb7cf 100644 --- a/src/soc/decoder/isa/caller.py +++ b/src/soc/decoder/isa/caller.py @@ -263,6 +263,17 @@ class SVP64RMFields: self.mode = FieldSelectableInt(self.spr, tuple(range(19,24))) +SVP64RM_MMODE_SIZE = len(SVP64RMFields().mmode.br) +SVP64RM_MASK_SIZE = len(SVP64RMFields().mask.br) +SVP64RM_ELWIDTH_SIZE = len(SVP64RMFields().elwidth.br) +SVP64RM_EWSRC_SIZE = len(SVP64RMFields().ewsrc.br) +SVP64RM_SUBVL_SIZE = len(SVP64RMFields().subvl.br) +SVP64RM_EXTRA2_SPEC_SIZE = len(SVP64RMFields().extra2[0].br) +SVP64RM_EXTRA3_SPEC_SIZE = len(SVP64RMFields().extra3[0].br) +SVP64RM_SMASK_SIZE = len(SVP64RMFields().smask.br) +SVP64RM_MODE_SIZE = len(SVP64RMFields().mode.br) + + # SVP64 Prefix fields: see https://libre-soc.org/openpower/sv/svp64/ class SVP64PrefixFields: def __init__(self): diff --git a/src/soc/sv/trans/svp64.py b/src/soc/sv/trans/svp64.py index 726bdacb..58404b53 100644 --- a/src/soc/sv/trans/svp64.py +++ b/src/soc/sv/trans/svp64.py @@ -18,8 +18,13 @@ import os, sys from collections import OrderedDict from soc.decoder.isa.caller import (SVP64PrefixFields, SV64P_MAJOR_SIZE, - SV64P_PID_SIZE, SV64P_RM_SIZE, - SVP64RMFields) + SV64P_PID_SIZE, SVP64RMFields, + SVP64RM_EXTRA2_SPEC_SIZE, + SVP64RM_EXTRA3_SPEC_SIZE, + SVP64RM_MODE_SIZE, SVP64RM_SMASK_SIZE, + SVP64RM_MMODE_SIZE, SVP64RM_MASK_SIZE, + SVP64RM_SUBVL_SIZE, SVP64RM_EWSRC_SIZE, + SVP64RM_ELWIDTH_SIZE) from soc.decoder.pseudo.pagereader import ISA from soc.decoder.power_svp64 import SVP64RM, get_regtype, decode_extra from soc.decoder.selectable_int import SelectableInt @@ -339,9 +344,11 @@ class SVP64Asm: for idx, sv_extra in extras.items(): if idx is None: continue if etype == 'EXTRA2': - svp64_rm.extra2[idx].eq(SelectableInt(sv_extra, 2)) + svp64_rm.extra2[idx].eq( + SelectableInt(sv_extra, SVP64RM_EXTRA2_SPEC_SIZE)) else: - svp64_rm.extra3[idx].eq(SelectableInt(sv_extra, 3)) + svp64_rm.extra3[idx].eq( + SelectableInt(sv_extra, SVP64RM_EXTRA3_SPEC_SIZE)) # parts of svp64_rm mmode = 0 # bit 0 @@ -509,25 +516,25 @@ class SVP64Asm: # now put into svp64_rm mode |= sv_mode # mode: bits 19-23 - svp64_rm.mode.eq(SelectableInt(mode, 5)) + svp64_rm.mode.eq(SelectableInt(mode, SVP64RM_MODE_SIZE)) # put in predicate masks into svp64_rm if ptype == '2P': # source pred: bits 16-18 - svp64_rm.smask.eq(SelectableInt(smask, 3)) + svp64_rm.smask.eq(SelectableInt(smask, SVP64RM_SMASK_SIZE)) # mask mode: bit 0 - svp64_rm.mmode.eq(SelectableInt(mmode, 1)) + svp64_rm.mmode.eq(SelectableInt(mmode, SVP64RM_MMODE_SIZE)) # 1-pred: bits 1-3 - svp64_rm.mask.eq(SelectableInt(pmask, 3)) + svp64_rm.mask.eq(SelectableInt(pmask, SVP64RM_MASK_SIZE)) # and subvl: bits 8-9 - svp64_rm.subvl.eq(SelectableInt(subvl, 2)) + svp64_rm.subvl.eq(SelectableInt(subvl, SVP64RM_SUBVL_SIZE)) # put in elwidths # srcwid: bits 6-7 - svp64_rm.ewsrc.eq(SelectableInt(srcwid, 2)) + svp64_rm.ewsrc.eq(SelectableInt(srcwid, SVP64RM_EWSRC_SIZE)) # destwid: bits 4-5 - svp64_rm.elwidth.eq(SelectableInt(destwid, 2)) + svp64_rm.elwidth.eq(SelectableInt(destwid, SVP64RM_ELWIDTH_SIZE)) # nice debug printout. (and now for something completely different) # https://youtu.be/u0WOIwlXE9g?t=146 -- 2.30.2