From b0177c83b5ff1549deab702c4cd2a506bb762fb6 Mon Sep 17 00:00:00 2001 From: Tobias Platen Date: Tue, 4 May 2021 20:32:39 +0200 Subject: [PATCH] upate dsisr and dar using sync --- src/soc/fu/mmu/fsm.py | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/src/soc/fu/mmu/fsm.py b/src/soc/fu/mmu/fsm.py index af92d68d..05d1f899 100644 --- a/src/soc/fu/mmu/fsm.py +++ b/src/soc/fu/mmu/fsm.py @@ -359,10 +359,11 @@ class FSMMMUStage(ControlBase): # subset SPR: first check a few bits with m.If(~spr[9] & ~spr[5]): comb += self.debug0.eq(3) + #if matched update local cached value with m.If(spr[0]): - comb += dsisr.eq(a_i[:32]) + sync += dsisr.eq(a_i[:32]) with m.Else(): - comb += dar.eq(a_i) + sync += dar.eq(a_i) comb += done.eq(1) # pass it over to the MMU instead with m.Else(): -- 2.30.2