From b0241d9f2de3dc23ed53903b296f30aee34bb5e4 Mon Sep 17 00:00:00 2001 From: Benjamin Herrenschmidt Date: Wed, 8 Jul 2020 14:00:27 +1000 Subject: [PATCH] corefile/nexys_video: Parameter fixes This fixes up a few issues with parameters: Only arty has "has_uart1" since we haven't added plumbing for a second UART anywhere else. Also "uart_is_16550" was mixing on one of the nexys_video targets, and nexys_video toplevel was missing LOG_LENGTH. Signed-off-by: Benjamin Herrenschmidt --- fpga/top-nexys-video.vhdl | 2 ++ microwatt.core | 4 +--- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/fpga/top-nexys-video.vhdl b/fpga/top-nexys-video.vhdl index 5395ff6..15fa176 100644 --- a/fpga/top-nexys-video.vhdl +++ b/fpga/top-nexys-video.vhdl @@ -20,6 +20,7 @@ entity toplevel is SPI_FLASH_OFFSET : integer := 10485760; SPI_FLASH_DEF_CKDV : natural := 1; SPI_FLASH_DEF_QUAD : boolean := true; + LOG_LENGTH : natural := 2048; UART_IS_16550 : boolean := true ); port( @@ -128,6 +129,7 @@ begin SPI_FLASH_OFFSET => SPI_FLASH_OFFSET, SPI_FLASH_DEF_CKDV => SPI_FLASH_DEF_CKDV, SPI_FLASH_DEF_QUAD => SPI_FLASH_DEF_QUAD, + LOG_LENGTH => LOG_LENGTH, UART0_IS_16550 => UART_IS_16550 ) port map ( diff --git a/microwatt.core b/microwatt.core index 046020d..15786fe 100644 --- a/microwatt.core +++ b/microwatt.core @@ -118,7 +118,6 @@ targets: - disable_flatten_core - log_length=2048 - uart_is_16550 - - has_uart1 tools: vivado: {part : xc7a100tcsg324-1} toplevel : toplevel @@ -135,7 +134,6 @@ targets: - spi_flash_offset=10485760 - log_length=2048 - uart_is_16550 - - has_uart1 tools: vivado: {part : xc7a200tsbg484-1} toplevel : toplevel @@ -151,6 +149,7 @@ targets: - no_bram - spi_flash_offset=10485760 - log_length=2048 + - uart_is_16550 generate: [litedram_nexys_video] tools: vivado: {part : xc7a200tsbg484-1} @@ -240,7 +239,6 @@ targets: - disable_flatten_core - log_length=512 - uart_is_16550 - - has_uart1 tools: vivado: {part : xc7a35tcpg236-1} toplevel : toplevel -- 2.30.2