From b0250d390e6133fb2a1c589515b2c3185f8559fc Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Thu, 4 Jun 2020 14:06:42 +0100 Subject: [PATCH] add rdmask and issue/busy setting --- src/soc/simple/core.py | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/src/soc/simple/core.py b/src/soc/simple/core.py index f3dee090..a6fc30ce 100644 --- a/src/soc/simple/core.py +++ b/src/soc/simple/core.py @@ -45,6 +45,8 @@ class NonProductionCore(Elaboratable): self.pdecode = pdecode = create_pdecode() self.pdecode2 = PowerDecode2(pdecode) # instruction decoder self.ivalid_i = self.pdecode2.e.valid # instruction is valid + self.issue_i = Signal(reset_less=True) + self.busy_o = Signal(reset_less=True) def elaborate(self, platform): m = Module() @@ -69,6 +71,10 @@ class NonProductionCore(Elaboratable): comb += enable.eq(self.ivalid_i & (dec2.e.fn_unit & fnunit).bool()) with m.If(enable): comb += fu.oper_i.eq_from_execute1(dec2.e) + comb += fu.issue_i.eq(self.issue_i) + comb += self.busy_o.eq(fu.busy_o) + rdmask = dec2.rdflags(fu) + comb += fu.rdmaskn.eq(~rdmask) comb += fu_bitdict[funame].eq(enable) # dictionary of lists of regfile read ports -- 2.30.2