From b03020435dc244f5d0a8edbe31b19421a4619542 Mon Sep 17 00:00:00 2001 From: Adrian Herrera Date: Mon, 17 Feb 2020 16:13:34 +0000 Subject: [PATCH] arch-arm: ArmISA::clear, inval TLB cached miscregs ArmISA::clear resets the value of the architecture registers. Some of these are cached in ArmTLB, including SCTLR. This patch invalidates the cached copies on clear; this fixes a bug when resetting CPU cores by which the cached SCTLR was used and SCTLR.M was set, resulting in non-arch compliant reset behaviour and a PA being treated as a VA on translation. Change-Id: I8d4eeeaf807325bd7b300a7a317abfa40ad23c87 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/25466 Reviewed-by: Jason Lowe-Power Maintainer: Giacomo Travaglini Tested-by: kokoro --- src/arch/arm/isa.cc | 9 +++++++++ src/arch/arm/isa.hh | 2 +- 2 files changed, 10 insertions(+), 1 deletion(-) diff --git a/src/arch/arm/isa.cc b/src/arch/arm/isa.cc index f6faf5b04..205f82f2d 100644 --- a/src/arch/arm/isa.cc +++ b/src/arch/arm/isa.cc @@ -119,6 +119,15 @@ ISA::params() const return dynamic_cast(_params); } +void +ISA::clear(ThreadContext *tc) +{ + clear(); + // Invalidate cached copies of miscregs in the TLBs + getITBPtr(tc)->invalidateMiscReg(); + getDTBPtr(tc)->invalidateMiscReg(); +} + void ISA::clear() { diff --git a/src/arch/arm/isa.hh b/src/arch/arm/isa.hh index 89be0158a..736c395a7 100644 --- a/src/arch/arm/isa.hh +++ b/src/arch/arm/isa.hh @@ -463,7 +463,7 @@ namespace ArmISA } public: - void clear(ThreadContext *tc) { clear(); } + void clear(ThreadContext *tc); protected: void clear(); -- 2.30.2