From b036f04cf0f952f894f9d86261030b44ebe010b4 Mon Sep 17 00:00:00 2001 From: Shriya Sharma Date: Mon, 25 Sep 2023 18:22:51 +0100 Subject: [PATCH] Added spaces and brackets for lhzu instruction --- openpower/isa/fixedload.mdwn | 14 +++++++++----- 1 file changed, 9 insertions(+), 5 deletions(-) diff --git a/openpower/isa/fixedload.mdwn b/openpower/isa/fixedload.mdwn index e9b4da88..94d59dd0 100644 --- a/openpower/isa/fixedload.mdwn +++ b/openpower/isa/fixedload.mdwn @@ -160,11 +160,15 @@ Pseudo-code: RT <- ([0] * (XLEN-16)) || MEM(EA, 2) RA <- EA -Description:Let the effective address (EA) be the sum (RA)+ D. The -halfword in storage addressed by EA is loaded into -RT48:63. RT 0:47 are set to 0. -EA is placed into register RA. -If RA=0 or RA=RT, the instruction form is invalid. +Description: + + Let the effective address (EA) be the sum (RA)+ D. The + halfword in storage addressed by EA is loaded into + RT[48:63]. RT[0:47] are set to 0. + + EA is placed into register RA. + + If RA=0 or RA=RT, the instruction form is invalid. Special Registers Altered: -- 2.30.2