From b04a756abb03cce48a1be84878c02c5a5bbe8b70 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Fri, 15 Mar 2019 17:49:39 +0100 Subject: [PATCH] vexriscv/core: fix min variant --- litex/soc/cores/cpu/vexriscv/core.py | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/litex/soc/cores/cpu/vexriscv/core.py b/litex/soc/cores/cpu/vexriscv/core.py index 1edcc3f7..3700bf44 100644 --- a/litex/soc/cores/cpu/vexriscv/core.py +++ b/litex/soc/cores/cpu/vexriscv/core.py @@ -155,8 +155,8 @@ class VexRiscv(Module, AutoCSR): "std_debug": "VexRiscv_Debug.v", "lite": "VexRiscv_Lite.v", "lite_debug": "VexRiscv_LiteDebug.v", - "min": "VexRiscv_Lite.v", - "min_debug": "VexRiscv_LiteDebug.v", + "min": "VexRiscv_Min.v", + "min_debug": "VexRiscv_MinDebug.v", } cpu_filename = verilog_variants[variant] vdir = os.path.join(os.path.abspath(os.path.dirname(__file__)), "verilog") -- 2.30.2