From b06f547993818224ded59c555345140199f4595f Mon Sep 17 00:00:00 2001 From: Miodrag Milanovic Date: Wed, 8 Dec 2021 11:50:10 +0100 Subject: [PATCH] If direction NONE use that from first bit --- frontends/verific/verific.cc | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/frontends/verific/verific.cc b/frontends/verific/verific.cc index dccdcb482..0548d9cb1 100644 --- a/frontends/verific/verific.cc +++ b/frontends/verific/verific.cc @@ -1112,6 +1112,13 @@ void VerificImporter::import_netlist(RTLIL::Design *design, Netlist *nl, std::se for (int i = portbus->LeftIndex();; i += portbus->IsUp() ? +1 : -1) { if (portbus->ElementAtIndex(i) && portbus->ElementAtIndex(i)->GetNet()) { + if (portbus->GetDir() == DIR_NONE && !wire->port_input && !wire->port_output) { + Port *p = portbus->ElementAtIndex(i); + if (p->GetDir() == DIR_INOUT || p->GetDir() == DIR_IN) + wire->port_input = true; + if (p->GetDir() == DIR_INOUT || p->GetDir() == DIR_OUT) + wire->port_output = true; + } net = portbus->ElementAtIndex(i)->GetNet(); RTLIL::SigBit bit(wire, i - wire->start_offset); if (net_map.count(net) == 0) -- 2.30.2