From b07042bfb1132455a1e0b7d82c6dd47071c0df57 Mon Sep 17 00:00:00 2001
From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Mon, 12 Oct 2020 12:58:34 +0100
Subject: [PATCH] use unittest.TestCase rather than FHDLTestCase

---
 src/nmutil/test/test_clz.py | 3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)

diff --git a/src/nmutil/test/test_clz.py b/src/nmutil/test/test_clz.py
index 1d066b4..09beb73 100644
--- a/src/nmutil/test/test_clz.py
+++ b/src/nmutil/test/test_clz.py
@@ -1,6 +1,5 @@
 from nmigen import Module, Signal
 from nmigen.back.pysim import Simulator, Delay
-from nmigen.test.utils import FHDLTestCase
 
 from nmutil.clz import CLZ
 import unittest
@@ -8,7 +7,7 @@ import math
 import random
 
 
-class CLZTestCase(FHDLTestCase):
+class CLZTestCase(unittest.TestCase):
     def run_test(self, inputs, width=8):
 
         m = Module()
-- 
2.30.2