From b0760a40bef3ca690691bf5d214da95b5dc25266 Mon Sep 17 00:00:00 2001 From: Richard Sandiford Date: Wed, 7 Aug 2019 19:05:42 +0000 Subject: [PATCH] [AArch64] Merge SVE reduction patterns The reorg showed that we had an unnecessary separation between the bitwise and max/min reductions for integers, and the addition and max/min reductions for fp. 2019-08-07 Richard Sandiford gcc/ * config/aarch64/iterators.md (BITWISEV): Delete. (SVE_INT_REDUCTION, SVE_FP_REDUCTION): New int iterators. (optab): Handle UNSPEC_UMAXV, UNSPEC_UMINV, UNSPEC_SMAXV, UNSPEC_SMINV, UNSPEC_FADDV, UNSPEC_FMAXNMV, UNSPEC_FMAXV, UNSPEC_FMINNMV, UNSPEC_FMINV. (bit_reduc_op): Delete. (sve_int_op): New int attribute. (sve_fp_op): Handle UNSPEC_FADDV, UNSPEC_FMAXNMV, UNSPEC_FMAXV, UNSPEC_FMINNMV, UNSPEC_FMINV. * config/aarch64/aarch64-sve.md (reduc__scal_) (*reduc__scal_) (reduc__scal_) (*reduc__scal_): Merge into... (reduc__scal_) (*reduc__scal_): ...these new patterns. (reduc_plus_scal_, *reduc_plus_scal_) (reduc__scal_) (*reduc__scal_): Merge into... (reduc__scal_) (*reduc__scal_): ...these new patterns. From-SVN: r274190 --- gcc/ChangeLog | 26 ++++++++++++ gcc/config/aarch64/aarch64-sve.md | 66 ++++++------------------------- gcc/config/aarch64/iterators.md | 44 +++++++++++++++++---- 3 files changed, 75 insertions(+), 61 deletions(-) diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 85d0dfee0dd..43e53c0a260 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,29 @@ +2019-08-07 Richard Sandiford + + * config/aarch64/iterators.md (BITWISEV): Delete. + (SVE_INT_REDUCTION, SVE_FP_REDUCTION): New int iterators. + (optab): Handle UNSPEC_UMAXV, UNSPEC_UMINV, UNSPEC_SMAXV, + UNSPEC_SMINV, UNSPEC_FADDV, UNSPEC_FMAXNMV, UNSPEC_FMAXV, + UNSPEC_FMINNMV, UNSPEC_FMINV. + (bit_reduc_op): Delete. + (sve_int_op): New int attribute. + (sve_fp_op): Handle UNSPEC_FADDV, UNSPEC_FMAXNMV, UNSPEC_FMAXV, + UNSPEC_FMINNMV, UNSPEC_FMINV. + * config/aarch64/aarch64-sve.md + (reduc__scal_) + (*reduc__scal_) + (reduc__scal_) + (*reduc__scal_): Merge into... + (reduc__scal_) + (*reduc__scal_): ...these + new patterns. + (reduc_plus_scal_, *reduc_plus_scal_) + (reduc__scal_) + (*reduc__scal_): Merge into... + (reduc__scal_) + (*reduc__scal_): ...these + new patterns. + 2019-08-07 Richard Sandiford * config/aarch64/aarch64-sve.md (fma4, *fma4) diff --git a/gcc/config/aarch64/aarch64-sve.md b/gcc/config/aarch64/aarch64-sve.md index 37a611c0462..3d60afacc25 100644 --- a/gcc/config/aarch64/aarch64-sve.md +++ b/gcc/config/aarch64/aarch64-sve.md @@ -3152,46 +3152,26 @@ "uaddv\t%d0, %1, %2." ) -;; Unpredicated integer MAX/MIN reduction. -(define_expand "reduc__scal_" - [(set (match_operand: 0 "register_operand") - (unspec: [(match_dup 2) - (match_operand:SVE_I 1 "register_operand")] - MAXMINV))] - "TARGET_SVE" - { - operands[2] = aarch64_ptrue_reg (mode); - } -) - -;; Predicated integer MAX/MIN reduction. -(define_insn "*reduc__scal_" - [(set (match_operand: 0 "register_operand" "=w") - (unspec: [(match_operand: 1 "register_operand" "Upl") - (match_operand:SVE_I 2 "register_operand" "w")] - MAXMINV))] - "TARGET_SVE" - "v\t%0, %1, %2." -) - +;; Unpredicated integer reductions. (define_expand "reduc__scal_" [(set (match_operand: 0 "register_operand") (unspec: [(match_dup 2) (match_operand:SVE_I 1 "register_operand")] - BITWISEV))] + SVE_INT_REDUCTION))] "TARGET_SVE" { operands[2] = aarch64_ptrue_reg (mode); } ) +;; Predicated integer reductions. (define_insn "*reduc__scal_" [(set (match_operand: 0 "register_operand" "=w") (unspec: [(match_operand: 1 "register_operand" "Upl") (match_operand:SVE_I 2 "register_operand" "w")] - BITWISEV))] + SVE_INT_REDUCTION))] "TARGET_SVE" - "\t%0, %1, %2." + "\t%0, %1, %2." ) ;; ------------------------------------------------------------------------- @@ -3205,48 +3185,26 @@ ;; - FMINV ;; ------------------------------------------------------------------------- -;; Unpredicated floating-point add reduction. -(define_expand "reduc_plus_scal_" - [(set (match_operand: 0 "register_operand") - (unspec: [(match_dup 2) - (match_operand:SVE_F 1 "register_operand")] - UNSPEC_FADDV))] - "TARGET_SVE" - { - operands[2] = aarch64_ptrue_reg (mode); - } -) - -;; Predicated floating-point add reduction. -(define_insn "*reduc_plus_scal_" - [(set (match_operand: 0 "register_operand" "=w") - (unspec: [(match_operand: 1 "register_operand" "Upl") - (match_operand:SVE_F 2 "register_operand" "w")] - UNSPEC_FADDV))] - "TARGET_SVE" - "faddv\t%0, %1, %2." -) - -;; Unpredicated floating-point MAX/MIN reduction. -(define_expand "reduc__scal_" +;; Unpredicated floating-point tree reductions. +(define_expand "reduc__scal_" [(set (match_operand: 0 "register_operand") (unspec: [(match_dup 2) (match_operand:SVE_F 1 "register_operand")] - FMAXMINV))] + SVE_FP_REDUCTION))] "TARGET_SVE" { operands[2] = aarch64_ptrue_reg (mode); } ) -;; Predicated floating-point MAX/MIN reduction. -(define_insn "*reduc__scal_" +;; Predicated floating-point tree reductions. +(define_insn "*reduc__scal_" [(set (match_operand: 0 "register_operand" "=w") (unspec: [(match_operand: 1 "register_operand" "Upl") (match_operand:SVE_F 2 "register_operand" "w")] - FMAXMINV))] + SVE_FP_REDUCTION))] "TARGET_SVE" - "v\t%0, %1, %2." + "\t%0, %1, %2." ) ;; ------------------------------------------------------------------------- diff --git a/gcc/config/aarch64/iterators.md b/gcc/config/aarch64/iterators.md index a6e2b1e6d27..5b72dc4147b 100644 --- a/gcc/config/aarch64/iterators.md +++ b/gcc/config/aarch64/iterators.md @@ -1501,8 +1501,6 @@ (define_int_iterator FMAXMINV [UNSPEC_FMAXV UNSPEC_FMINV UNSPEC_FMAXNMV UNSPEC_FMINNMV]) -(define_int_iterator BITWISEV [UNSPEC_ANDV UNSPEC_IORV UNSPEC_XORV]) - (define_int_iterator LOGICALF [UNSPEC_ANDF UNSPEC_IORF UNSPEC_XORF]) (define_int_iterator HADDSUB [UNSPEC_SHADD UNSPEC_UHADD @@ -1612,6 +1610,20 @@ (define_int_iterator MUL_HIGHPART [UNSPEC_SMUL_HIGHPART UNSPEC_UMUL_HIGHPART]) +(define_int_iterator SVE_INT_REDUCTION [UNSPEC_ANDV + UNSPEC_IORV + UNSPEC_SMAXV + UNSPEC_SMINV + UNSPEC_UMAXV + UNSPEC_UMINV + UNSPEC_XORV]) + +(define_int_iterator SVE_FP_REDUCTION [UNSPEC_FADDV + UNSPEC_FMAXV + UNSPEC_FMAXNMV + UNSPEC_FMINV + UNSPEC_FMINNMV]) + (define_int_iterator SVE_COND_FP_UNARY [UNSPEC_COND_FABS UNSPEC_COND_FNEG UNSPEC_COND_FRINTA @@ -1682,6 +1694,15 @@ (UNSPEC_ANDV "and") (UNSPEC_IORV "ior") (UNSPEC_XORV "xor") + (UNSPEC_UMAXV "umax") + (UNSPEC_UMINV "umin") + (UNSPEC_SMAXV "smax") + (UNSPEC_SMINV "smin") + (UNSPEC_FADDV "plus") + (UNSPEC_FMAXNMV "smax") + (UNSPEC_FMAXV "smax_nan") + (UNSPEC_FMINNMV "smin") + (UNSPEC_FMINV "smin_nan") (UNSPEC_COND_FABS "abs") (UNSPEC_COND_FADD "add") (UNSPEC_COND_FDIV "div") @@ -1731,10 +1752,6 @@ (UNSPEC_FMAXNM "fmaxnm") (UNSPEC_FMINNM "fminnm")]) -(define_int_attr bit_reduc_op [(UNSPEC_ANDV "andv") - (UNSPEC_IORV "orv") - (UNSPEC_XORV "eorv")]) - ;; The SVE logical instruction that implements an unspec. (define_int_attr logicalf_op [(UNSPEC_ANDF "and") (UNSPEC_IORF "orr") @@ -1932,7 +1949,20 @@ (UNSPEC_COND_FCMLT "lt") (UNSPEC_COND_FCMNE "ne")]) -(define_int_attr sve_fp_op [(UNSPEC_COND_FABS "fabs") +(define_int_attr sve_int_op [(UNSPEC_ANDV "andv") + (UNSPEC_IORV "orv") + (UNSPEC_XORV "eorv") + (UNSPEC_UMAXV "umaxv") + (UNSPEC_UMINV "uminv") + (UNSPEC_SMAXV "smaxv") + (UNSPEC_SMINV "sminv")]) + +(define_int_attr sve_fp_op [(UNSPEC_FADDV "faddv") + (UNSPEC_FMAXNMV "fmaxnmv") + (UNSPEC_FMAXV "fmaxv") + (UNSPEC_FMINNMV "fminnmv") + (UNSPEC_FMINV "fminv") + (UNSPEC_COND_FABS "fabs") (UNSPEC_COND_FADD "fadd") (UNSPEC_COND_FDIV "fdiv") (UNSPEC_COND_FMAXNM "fmaxnm") -- 2.30.2