From b07ffbf8be6f46c4e6c15dfb262bae712e00370f Mon Sep 17 00:00:00 2001 From: lkcl Date: Sun, 14 Aug 2022 17:03:55 +0100 Subject: [PATCH] --- openpower/sv/cr_ops.mdwn | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/openpower/sv/cr_ops.mdwn b/openpower/sv/cr_ops.mdwn index 54514b7c5..45e54f224 100644 --- a/openpower/sv/cr_ops.mdwn +++ b/openpower/sv/cr_ops.mdwn @@ -71,7 +71,8 @@ SVP64 RM `MODE` (includes `ELWIDTH_SRC` bits) for CR-based operations: | 6 | 7 | 19-20 | 21 | 22 23 | description | | - | - | ----- | --- |---------|----------------- | -|sz |SNZ| 0 RG | 0 | dz / | normal mode | +|sz |SNZ| 0 RG | 0 | dz 0 | normal mode | +|sz |SNZ| 0 RG | 0 | dz 1 | Pack/Unpack mode | |sz |SNZ| 0 RG | 1 | 0 / | scalar reduce mode (mapreduce), SUBVL=1 | |zz |SNZ| 0 RG | 1 | 1 / | parallel reduce mode (mapreduce), SUBVL=1 | |sz |SNZ| 0 RG | 1 | SVM / | subvector reduce mode, SUBVL>1 | -- 2.30.2