From b09162163b732c85aa03f389e64a2fbdccae6241 Mon Sep 17 00:00:00 2001 From: lkcl Date: Tue, 22 Dec 2020 14:19:29 +0000 Subject: [PATCH] --- openpower/sv/vector_ops.mdwn | 3 +++ 1 file changed, 3 insertions(+) diff --git a/openpower/sv/vector_ops.mdwn b/openpower/sv/vector_ops.mdwn index c3dce25db..b73639e82 100644 --- a/openpower/sv/vector_ops.mdwn +++ b/openpower/sv/vector_ops.mdwn @@ -3,6 +3,9 @@ The core OpenPOWER ISA was designed as scalar: SV provides a level of abstraction to add variable-length element-independent parallelism. However, certain classes of instructions only make sense in a Vector context: AVC512 conflictd for example. This section includes such examples. Many of them are from the RISC-V Vector ISA (with thanks to the efforts of RVV's contributors) However some of these actually could be added to a scalar ISA as bitmanipulation instructions. These are separated out into their own section. +Instructions suited to 3D GPU workloads (dotproduct, crossproduct, normalise) are out of scope: this document is for more general-purpose instructions that underpin and are critical to general-purpose Vector workloads (including GPU and VPU) + +. Links: * -- 2.30.2