From b0f16cf896c5888893ec3326fbfa4a4e584552dd Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Wed, 22 Dec 2021 00:49:07 +0000 Subject: [PATCH] clear instruction fault on exception WAIT_MMU ACK in LoadStore1 --- src/soc/fu/ldst/loadstore.py | 1 + 1 file changed, 1 insertion(+) diff --git a/src/soc/fu/ldst/loadstore.py b/src/soc/fu/ldst/loadstore.py index 8ad751e7..eb452dbf 100644 --- a/src/soc/fu/ldst/loadstore.py +++ b/src/soc/fu/ldst/loadstore.py @@ -255,6 +255,7 @@ class LoadStore1(PortInterfaceBase): # XXX there is no architected bit for this # (probably should be a machine check in fact) sync += self.dsisr[63 - 35].eq(d_in.cache_paradox) + sync += self.r_instr_fault.eq(0) with m.Else(): # Look up the translation for TLB miss -- 2.30.2