From b0f39f7e61cce2d2e0d948ab26c48745128d983f Mon Sep 17 00:00:00 2001 From: lkcl Date: Fri, 11 Dec 2020 02:11:15 +0000 Subject: [PATCH] --- openpower/sv/svp_rewrite/svp64/discussion.mdwn | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/openpower/sv/svp_rewrite/svp64/discussion.mdwn b/openpower/sv/svp_rewrite/svp64/discussion.mdwn index 08a6ab833..edb6802fd 100644 --- a/openpower/sv/svp_rewrite/svp64/discussion.mdwn +++ b/openpower/sv/svp_rewrite/svp64/discussion.mdwn @@ -35,6 +35,18 @@ something like: * vspec - 3 bit src / dest scalar-vector extension * sat: 0bSU - S=1 signed U=1 unsigned 0b11 reserved +## twin predication, CR based. + +separate src and dest predicates are a critical part of SV for provision of VGATHER, VSCATTER, VREDUCE, VSPLAT and many more operations. + +Twin CR predication could be done in two ways: + +* start from different CRs for the src and dest +* start from the same CR. + +With different bits being selectable (CR[0..3]) starting from the same CR makes some sense. + + # standard arith ops (single predication) these are of the form res = op(src1, src2, ...) -- 2.30.2