From b0f4095859ec378abe466dbb2480e3bd5b8d70a0 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Tue, 2 Jun 2020 21:15:35 +0100 Subject: [PATCH] decode fast spr for OP_BCREG CTR, TAR and LR --- src/soc/decoder/power_decoder2.py | 13 ++++++++++--- src/soc/fu/branch/test/test_pipe_caller.py | 2 +- src/soc/fu/compunits/test/test_branch_compunit.py | 10 +--------- src/soc/regfile/util.py | 10 ++++++++++ 4 files changed, 22 insertions(+), 13 deletions(-) create mode 100644 src/soc/regfile/util.py diff --git a/src/soc/decoder/power_decoder2.py b/src/soc/decoder/power_decoder2.py index e50d1ca5..76188bf7 100644 --- a/src/soc/decoder/power_decoder2.py +++ b/src/soc/decoder/power_decoder2.py @@ -62,8 +62,10 @@ class DecodeA(Elaboratable): # BC or BCREG: potential implicit register (CTR) NOTE: same in DecodeOut with m.If((op.internal_op == InternalOp.OP_BC) | (op.internal_op == InternalOp.OP_BCREG)): + xo9 = self.dec.FormXL.XO[9] # 3.0B p38 top bit of XO + xo5 = self.dec.FormXL.XO[5] # 3.0B p38 with m.If(~self.dec.BO[2] | # 3.0B p38 BO2=0, use CTR reg - self.dec.FormXL.XO[9]): # 3.0B p38 top bit of XO + (xo9 & ~xo5)): comb += self.fast_out.data.eq(FastRegs.CTR) # constant: CTR comb += self.fast_out.ok.eq(1) @@ -157,13 +159,18 @@ class DecodeB(Elaboratable): # decode SPR2 based on instruction type op = self.dec.op - # BCREG implicitly uses LR or TAR for 2nd reg (TODO: TAR) + # BCREG implicitly uses LR or TAR for 2nd reg # CTR however is already in fast_spr1 *not* 2. with m.If((op.internal_op == InternalOp.OP_BC) | (op.internal_op == InternalOp.OP_BCREG)): - with m.If(~self.dec.FormXL.XO[9]): # 3.0B p38 top bit of XO + xo9 = self.dec.FormXL.XO[9] # 3.0B p38 top bit of XO + xo5 = self.dec.FormXL.XO[5] # 3.0B p38 + with m.If(~xo9): comb += self.fast_out.data.eq(FastRegs.LR) comb += self.fast_out.ok.eq(1) + with m.Elif(xo5): + comb += self.fast_out.data.eq(FastRegs.TAR) + comb += self.fast_out.ok.eq(1) return m diff --git a/src/soc/fu/branch/test/test_pipe_caller.py b/src/soc/fu/branch/test/test_pipe_caller.py index aa544c66..c14ed974 100644 --- a/src/soc/fu/branch/test/test_pipe_caller.py +++ b/src/soc/fu/branch/test/test_pipe_caller.py @@ -16,7 +16,7 @@ from soc.fu.branch.pipeline import BranchBasePipe from soc.fu.branch.pipe_data import BranchPipeSpec import random -from soc.compunits.test.test_branch_compunit import fast_reg_to_spr # HACK! +from soc.regfile.util import fast_reg_to_spr # HACK! class TestCase: def __init__(self, program, regs, sprs, cr, name): diff --git a/src/soc/fu/compunits/test/test_branch_compunit.py b/src/soc/fu/compunits/test/test_branch_compunit.py index 312d3348..0c84d94b 100644 --- a/src/soc/fu/compunits/test/test_branch_compunit.py +++ b/src/soc/fu/compunits/test/test_branch_compunit.py @@ -8,20 +8,12 @@ from soc.fu.branch.test.test_pipe_caller import test_data from soc.fu.compunits.compunits import BranchFunctionUnit from soc.fu.compunits.test.test_compunit import TestRunner -from soc.regfile.regfiles import FastRegs +from soc.regfile.util import fast_reg_to_spr # HACK! """ def assert_outputs(self, branch, dec2, sim, prev_nia, code): """ -def fast_reg_to_spr(spr_num): - if spr_num == FastRegs.CTR: - return SPR.CTR.value - elif spr_num == FastRegs.LR: - return SPR.LR.value - elif spr_num == FastRegs.TAR: - return SPR.TAR.value - class BranchTestRunner(TestRunner): def __init__(self, test_data): diff --git a/src/soc/regfile/util.py b/src/soc/regfile/util.py new file mode 100644 index 00000000..f27d711e --- /dev/null +++ b/src/soc/regfile/util.py @@ -0,0 +1,10 @@ +from soc.regfile.regfiles import FastRegs +from soc.decoder.power_enums import SPR + +def fast_reg_to_spr(spr_num): + if spr_num == FastRegs.CTR: + return SPR.CTR.value + elif spr_num == FastRegs.LR: + return SPR.LR.value + elif spr_num == FastRegs.TAR: + return SPR.TAR.value -- 2.30.2