From b0fbc4a9df0e5c174f2be6073f93952c2e0058b0 Mon Sep 17 00:00:00 2001
From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Fri, 29 Apr 2022 10:33:43 +0100
Subject: [PATCH] invert RC and RA, making divmod2du more like divdu not divdeu

---
 openpower/isa/svfixedarith.mdwn | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/openpower/isa/svfixedarith.mdwn b/openpower/isa/svfixedarith.mdwn
index ebef59ce..cf883450 100644
--- a/openpower/isa/svfixedarith.mdwn
+++ b/openpower/isa/svfixedarith.mdwn
@@ -18,7 +18,7 @@ Special Registers Altered:
 
     None
 
-# [DRAFT] Twin Divide Quad Unsigned
+# [DRAFT] Twin Divide/Modulo Quad Unsigned
 
 VA-Form
 
@@ -30,7 +30,7 @@ Pseudo-code:
     <!-- bit 8 of EXTRA is clear: RS.[s|v]=RT.[s|v]+VL -->
     <!-- bit 8 of EXTRA is set  : RS.[s|v]=RC.[s|v]    -->
     if ((RA) <u (RB)) & ((RB) != [0]*XLEN) then
-        dividend[0:(XLEN*2)-1] <- (RA) || (RC)
+        dividend[0:(XLEN*2)-1] <- (RC) || (RA)
         divisor[0:(XLEN*2)-1] <- [0]*XLEN || (RB)
         result <- dividend / divisor
         modulo <- dividend % divisor
-- 
2.30.2